#include "fpga_manage.h"
#include <unistd.h>
#include <math.h>
#include "onbonsource.h"
#include "messageDeal/message_deal.h"
#include "../utils/utils.h"
#include "global.h"
#include <boost/property_tree/json_parser.hpp>  
// #include "/home/ttzt/linux/buildroot/buildroot-2023.02/mt-out/host/aarch64-buildroot-linux-gnu/sysroot/usr/include/boost/json_parser.hpp"
// #include <libcfgclient.h>

using namespace boost::property_tree;



#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <fcntl.h>
#include "../global/BxGlobal.h"

fpga_manage *fpga_manage::p_fpga_manage = NULL ;

Ouint8 * fpga_manage::MCU_REG_func[1] = {NULL} ;
Ouint8 * fpga_manage::MCU_RAM_PARA_func[1] = {NULL} ;
Ouint8 * fpga_manage::MCU_RAM_RX_func[1] = {NULL} ;
Ouint8 * fpga_manage::MCU_RAM_TX_func[1] = {NULL} ;
Ouint8 * fpga_manage::MCU_RAM_ETH_PARA_func[1] = {NULL}  ;
Ouint8 * fpga_manage::MCU_RAM_ETH_BACK_PARA_func[1] = {NULL}  ;
Ouint8 fpga_manage::MCU_RAM_DEFAULT[FPGA_RAM_DEFAULT_LEN] ;
Ouint8 fpga_manage::MCU_RAM_ZOOM[FPGA_RAM_MAX_LEN] ;
Ouint8 fpga_manage::MCU_RAM_CMD[FPGA_RAM_MAX_LEN] ;
Ouint8 fpga_manage::MCU_RAM_EXTEND[FPGA_RAM_MAX_LEN] ;

//网口参数默认为 1280*720
const Ouint8 fpga_manage::RAM1[256] = {
    /** 000 - 015**/    0x00,0x05,0x00,0x04,0x76,0x05,0xD2,0x01,0x00,0x00,0x00,0x00,0x00,0x05,0x00,0x02,
    /** 016 - 031**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x00,0x02,0x00,0x00,0x00,0x02,0x00,
    /** 032 - 047**/    0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 048 - 063**/    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x00,0x04,
    /** 064 - 079**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 080 - 095**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 096 - 111**/    0x05,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 112 - 127**/    0x00,0x00,0x00,0x00,0x56,0x05,0x00,0x03,0xD9,0xB8,0x0C,0x00,0x00,0x00,0x00,0x00,
    /** 128 - 143**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 144 - 159**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 160 - 175**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 176 - 191**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 192 - 207**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 208 - 223**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 224 - 239**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /** 240 - 255**/    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
};


Ouint8  fpga_manage::SEND_READ_VMF_RAM0_CMD[19]={0xFE,0x0F,0x00,0xF0,0x10,0xBB,0x03,0x00,0x00,0x61,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00};//读取RAM0区参数
Ouint8  fpga_manage::SEARCH_CARD_BUF[15]={0xFE,0x0F,0x00,0xF0,0x10,0xAA,0xFF,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00};//网口搜索卡命令
Ouint8  fpga_manage::SEND_BRI_ETH_CMD[20]={0xFE,0x0F,0x00,0xF0,0x10,0x66,0x01,0x00,0x00,0x60,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xFF,0x00};//网口调亮值写入
Ouint8  fpga_manage::SEND_BRI_ETH_REG[15]={0xFE,0x0F,0x00,0xF0,0x10,0x66,0x01,0x00,0x00,0xA0,0x01,0x08,0x00,0x08,0x00};//网口调亮值写入
Ouint8  fpga_manage::SEND_BRI_SAVE_CMD[13]={0xFE,0x0F,0x00,0xF0,0x10,0x66,0x01,0x00,0x00,0x81,0x09,0x00,0x00};//网口调亮值写入
Ouint8  fpga_manage::HalfHourValue[48] = { 0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,
                                          0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,
                                          0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f};
//#define DRV_FPGA1_IRQ_VBYONE_NAME "/sys/class/gpio/gpio87/value"
//#define DRV_FPGA2_IRQ_VBYONE_NAME "/sys/class/gpio/gpio89/value"




/*copy to kernel/drivers/sstar/include*/
#define MSYS_IOCTL_MAGIC 'S'
#define IOCTL_MSYS_GET_RIU_MAP _IO(MSYS_IOCTL_MAGIC, 0x15)

#define IOCTL_MSYS_VERSION    0x0100
#define VERCHK_HEADER       0x4D530000
#define VERCHK_HADER_MASK   0xFFFF0000
#define VERCHK_VERSION_MASK 0x0000FFFF
#define VERCHK_MAJORVERSION_MASK 0x0000FF00

//!! 管脚基地址
#define GPIO2IOMUX 0XFDC60000
#define GPIO2DIOOFFSET 0X0038
#define GPIO2DPADOFFSET 0X

//!！ gpio 寄存器
#define GPIO0_REG_BASE 0xFDD60000   //GPIO0
#define GPIO1_REG_BASE 0xFE740000
#define GPIO2_REG_BASE 0xFE750000   //GPIO2_D6 === MCU_CTLA_CMD1
#define GPIO3_REG_BASE 0xFE760000   //GPIO3_B2 === FPGA_PROGRAMN1
#define GPIO4_REG_BASE 0xFE770000

//!! 控制GPIO输出高低寄存器地址偏移
#define GPIO_SWPORT_DR_L_OFFSET 0x0000
#define GPIO_SWPORT_DR_H_OFFSET 0x0004
//!! 控制GPIO输入输出寄存器偏移
#define GPIO_SWPORT_DDR_L_OFFSET 0x0008
#define GPIO_SWPORT_DDR_H_OFFSET 0x000c
//!! GPIO读状态下获取外部信号状态寄存器偏移
#define GPIO_EXT_PORT  0x0070



#define SIZE_MAP 0x1000

#define FILL_VERCHK_TYPE(var, var_ver, var_size, version)        \
    ({                                                               \
    var_ver = (VERCHK_HEADER | (version & VERCHK_VERSION_MASK)); \
    var_size = sizeof(var);                                      \
    var;                                                         \
    })




#define P_ONBONFPGAMANAGETHIS                    ((fpga_manage*)p_about_fpga_manage)

Rcv_Card_Send_Para g_send_para;
SCAN_PARA scan_para;

fpga_manage::fpga_manage()
{
    m_memFd = -1;
    m_baseGpio0 = NULL;
    m_baseGpio1 = NULL;
    m_baseGpio2 = NULL;
    m_baseGpio3 = NULL;
    m_baseGpio4 = NULL;

    BX_printf("====fpga_manage::fpga_manage()=====\n");
    p_fpga_drv = new fpga_drv();
    MCU_REG_func[FPGA_MASTER_VBYONE1] = MCU_REG_VBYONE1 ;

    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1] = MCU_RAM_PARA_VBYONE1 ;

    MCU_RAM_RX_func[FPGA_MASTER_VBYONE1]= MCU_RAM_RX_VBYONE1;

    MCU_RAM_TX_func[FPGA_MASTER_VBYONE1]= MCU_RAM_TX_VBYONE1;

    MCU_RAM_ETH_PARA_func[FPGA_MASTER_VBYONE1] = MCU_RAM_ETH_VBYONE1;

    MCU_RAM_ETH_BACK_PARA_func[FPGA_MASTER_VBYONE1] = MCU_RAM_ETH_BACK_VBYONE1;

    check_fpga_phy_status[FPGA_MASTER_VBYONE1] = FPGA_PHY_INIT_START;

    green_check_ok[FPGA_MASTER_VBYONE1] = 0;

    fpga_init_step[FPGA_MASTER_VBYONE1] = FPGA_VBO_INIT_START;

    fpga_init_error[FPGA_MASTER_VBYONE1] = 0x00;

    fpga_init_rst_times[FPGA_MASTER_VBYONE1] = 0x00;

    fpga_vbo_status[FPGA_MASTER_VBYONE1] = 0x00;

    g_lcd_change[FPGA_MASTER_VBYONE1] = 3;

    g_dvi_count[FPGA_MASTER_VBYONE1] = 0;

    check_frame_stable[FPGA_MASTER_VBYONE1] = 0;

    check_frame_reset[FPGA_MASTER_VBYONE1] = 0;
    rcv_unlocksend_over = 0;
    rcv_locksend_over = 0;
    check_fpga_ram_status[FPGA_MASTER_VBYONE1] = false;



    passby_trans_port_over = 0;


    pthread_mutex_init(&m_fpga_reg, NULL);
    pthread_mutex_init(&m_fpga_manage, NULL);



}




fpga_manage::~fpga_manage()
{
    if(m_memFd != -1){
        close(m_memFd);
        m_memFd = -1;
    }
    if(m_baseGpio0 != NULL){
        munmap(m_baseGpio0, SIZE_MAP);
        m_baseGpio0 = NULL;
    }
    if(m_baseGpio1 != NULL){
        munmap(m_baseGpio1, SIZE_MAP);
        m_baseGpio1 = NULL;
    }
    if(m_baseGpio2 != NULL){
        munmap(m_baseGpio2, SIZE_MAP);
        m_baseGpio2 = NULL;
    }
    if(m_baseGpio3 != NULL){
        munmap(m_baseGpio3, SIZE_MAP);
        m_baseGpio3 = NULL;
    }
    if(m_baseGpio4 != NULL){
        munmap(m_baseGpio4, SIZE_MAP);
        m_baseGpio4 = NULL;
    }
}



fpga_manage* fpga_manage::pInstance()
{
    if(p_fpga_manage == NULL){
        p_fpga_manage = new fpga_manage();

        p_fpga_manage->initialize();
    }
    return p_fpga_manage;
}


Oint8 fpga_manage::initialize()
{
    //创建时间线程
    pthread_t tid;
    pthread_create(&tid, NULL, timeThread, this);
    if(0 != pthread_create(&tid, NULL, timeThread, this))
    {
        BX_printf("create timeThread failed\n");
        return -1;
    }

    unsigned int bank,offset;

    fpga_vbyone1_fd = p_fpga_drv->initialize_vbyne1(FPGA_MASTER_VBYONE1);
    fpga_vbyone1_flash_fd = p_fpga_drv->initialize_vbyne1(FPGA_FLASH_VBYONE1);
    //FILL_VERCHK_TYPE(m_info, m_info.VerChk_Version, m_info.VerChk_Size, IOCTL_MSYS_VERSION);

    // setGpioInOutPut(3, 20, 0); //!! GPIO3 C4 GPIO输入功能 FPGA2_CTL1_INT1
    // setGpioInOutPut(2, 30, 1); //!! GPIO2 D6 GPIO输出功能 mcu_cmd

    //flash 1 sel
    // setGpioInOutPut(3, 1, 1);
    setGpioHigLow(3, 1, 1);

    // setGpioInOutPut(3, 10, 1); //!! GPIO3 B2 GPIO输出功能 program
    setGpioHigLow(3, 10, 0);
    usleep(1000*100);
    setGpioHigLow(3, 10, 1);

    softinit();
    usleep(1000*1000*2);
    g_fpga_c331_start = 0;

#if 1
    //    *(unsigned short *)to_fpga1_reset = GPIO17_CONTENT_H;
    //创建管理线程
    if(0 != pthread_create(&m_pidfpgamanage, NULL, fpgamanageThread, this))
    {
        BX_printf("create manage thread failed\n");
        return -1;
    }
#endif

    return 0;
}

//计数线程
void * fpga_manage::timeThread(void *arg )
{
    do{
        usleep(10 * 1000);
        G_timeTicks++;
        if(G_timeTicks > 0x8ffffff){
                G_timeTicks = 0;
            }
    }while (!g_AppExit);
    return NULL;
}

Oint8 fpga_manage::setMmapHig(Oint8* addr, Ouint32 value)
{
    Ouint32 regValue = (Ouint32)(*addr);
    (*addr) = regValue | value;

    return 0;
}


Oint8 fpga_manage::setMmapLow(Oint8* addr, Ouint32 value)
{
    Ouint32 regValue = (Ouint32)(*addr);
    (*addr) = regValue & value;

    return 0;
}

Oint8* fpga_manage::getMmapAddr(Ouint8 block)
{
    Oint8 *ret = NULL;
    Ouint32 baseAddr = 0;
    if (-1 == m_memFd)
    {
        m_memFd = open("/dev/mem", O_RDWR | O_SYNC);
        if(m_memFd < 0){
            m_memFd = -1;
            return NULL;
        }
    }

    switch(block){
    case 0:{
        if(m_baseGpio0 == NULL){
            m_baseGpio0 = (Oint8*)mmap(NULL, SIZE_MAP, PROT_READ | PROT_WRITE, MAP_SHARED, m_memFd, GPIO0_REG_BASE);
            if (m_baseGpio0 == 0)
            {
                printf("\n gpio0 mmap NULL pointer!\n");
                ret = NULL;
            }else{
                ret = m_baseGpio0;
            }
        }else {
            ret = m_baseGpio0;
        }
    }break;
    case 1:{
        if(m_baseGpio1 == NULL){
            m_baseGpio1 = (Oint8*)mmap(NULL, SIZE_MAP, PROT_READ | PROT_WRITE, MAP_SHARED, m_memFd, GPIO1_REG_BASE);
            if (m_baseGpio1 == 0)
            {
                printf("\n gpio1 mmap NULL pointer!\n");
                ret = NULL;
            }else{
                ret = m_baseGpio1;
            }
        }else {
            ret = m_baseGpio1;
        }
    }break;
    case 2:{
        if(m_baseGpio2 == NULL){
            m_baseGpio2 = (Oint8*)mmap(NULL, SIZE_MAP, PROT_READ | PROT_WRITE, MAP_SHARED, m_memFd, GPIO2_REG_BASE);
            if (m_baseGpio2 == 0)
            {
                printf("\n gpio2 mmap NULL pointer!\n");
                ret = NULL;
            }else{
                printf("test =====m_baseGpio2===== 0x%x \n", m_baseGpio2);
                ret = m_baseGpio2;
            }
        }else {
            ret = m_baseGpio2;
        }
    }break;
    case 3:{
        if(m_baseGpio3 == NULL){
            m_baseGpio3 = (Oint8*)mmap(NULL, SIZE_MAP, PROT_READ | PROT_WRITE, MAP_SHARED, m_memFd, GPIO3_REG_BASE);
            if (m_baseGpio3 == 0)
            {
                printf("\n gpio3 mmap NULL pointer!\n");
                ret = NULL;
            }else{
                printf("test =====m_baseGpio3===== 0x%x \n", m_baseGpio3);
                ret = m_baseGpio3;
            }
        }else {
            ret = m_baseGpio3;
        }
    }break;
    case 4:{
        if(m_baseGpio4 == NULL){
            m_baseGpio4 = (Oint8*)mmap(NULL, SIZE_MAP, PROT_READ | PROT_WRITE, MAP_SHARED, m_memFd, GPIO4_REG_BASE);
            if (m_baseGpio4 == 0)
            {
                printf("\n gpio4 mmap NULL pointer!\n");
                ret = NULL;
            }else{
                ret = m_baseGpio4;
            }
        }else {
            ret = m_baseGpio4;
        }
    }break;
    default:{
        return NULL;
    }
    }

    return ret;
}


/**
 * @brief fpga_manage::setGpioInOutPut
 * @param block 是哪一组GPIO
 * @param number 是当前组中的第几个gpio（A0-B0-C0-D0-D7分别对应32个GPIO）
 * @param value 0：GPIO输入 1：GPIO输出
 * @return 0 成功 其他失败
 */
Oint8 fpga_manage::setGpioInOutPut(Ouint8 block, Ouint8 number, Obool value)
{
    Ouint32 ioValue = 1;
    Ouint32 dtsValue = 0;

    if(block > 4){ //! 当前RK3568有5组GPIO（0--4）
        printf("Exceeds the current GPIO group number !! \n");
        return -1;
    }

    if(number > 31){ //! 每组GPIO最多32个（0--31）
        printf("Exceeds the current GPIO number !! \n");
        return -1;
    }

    Oint8* baseAddr = getMmapAddr(block);

    if(baseAddr == NULL){
        return -1;
    }

    if(number >= 16){
        number -= 16;
        baseAddr  += GPIO_SWPORT_DDR_H_OFFSET;
    }else {
        baseAddr  += GPIO_SWPORT_DDR_L_OFFSET;
    }

    //!! 取出原寄存器的数值；
    dtsValue = *(volatile Ouint32 *)baseAddr;
    ioValue = (ioValue << number) | (ioValue << (number + 16));

    if(value){
        //!! GPIO为输出状态
        //!! 计算出当前GPIO对应的bit位
        dtsValue = dtsValue | ioValue ;
    }else{
        //!! GPIO为输入状态
        dtsValue = dtsValue & (~ioValue) ;
        ioValue = 1;
        ioValue = ioValue << (number + 16);
        dtsValue = dtsValue | ioValue ;
    }
    *(volatile Ouint32 *)baseAddr = dtsValue;

    return 0;
}

int fpga_manage::mcu_ctla_cmd1_setlevel(int num)
{
    int fd;
    char level[2];
    int ret;

    // printf("mcu_ctla_cmd1\n");
    sprintf(level, "%d", num);

    fd = open("/sys/devices/platform/gpioctrl/mcu_ctla_cmd1", O_RDWR);
    // printf("fd: %d\n", fd);
    if (fd < 0)
    {
        perror("open mcu_ctla_cmd1 error\n");
        close(fd);
        return fd;
    }
    else
    {
        // perror("open mcu_ctla_cmd1 success\n");
    }
    ret = write(fd, level, 1);
    if (ret < 0)
    {
        perror("write mcu_ctla_cmd1 error\n");
        close(fd);
        return ret;
    }

    close(fd);
    return 0;
}

int fpga_manage::flash_sel1_setlevel(int num)
{
    int fd;
    char level[2];

    // printf("flashsel1_setlevel\n");
    sprintf(level, "%d", num);

    fd = open("/sys/devices/platform/gpioctrl/flash_sel1", O_RDWR);
    // printf("fd: %d\n", fd);
    if (fd < 0)
    {
        perror("open flashsel1 error\n");
        close(fd);
        return fd;
    }
    else
    {
        // perror("open flashsel1 success\n");
    }
    write(fd, level, 1);
    close(fd);
    return 0;
}

int fpga_manage::fpga_program1_setlevel(int num)
{
    int fd;
    char level[2];

    // printf("fpga_program1_setlevel\n");
    sprintf(level, "%d", num);

    fd = open("/sys/devices/platform/gpioctrl/fpga_programn1", O_RDWR);
    // printf("fd: %d\n", fd);
    if (fd < 0)
    {
        perror("open fpga_program1 error\n");
        close(fd);
        return fd;
    }
    else
    {
        // perror("open fpga_program1 success\n");
    }
    write(fd, level, 1);
    close(fd);
    return 0;
}



/**
 * @brief fpga_manage::setGpioHigLow
 * @param block 是哪一组GPIO
 * @param number 是当前组中的第几个gpio（A0-B0-C0-D0-D7分别对应32个GPIO）
 * @param value 0：GPIO输出底 1：GPIO输出高
 * @return 0 成功 其他失败
 * @return
 */
#if 0
    Oint8 fpga_manage::setGpioHigLow(Ouint8 block, Ouint8 number, int value)
    {
        Ouint32 ioValue = 1;
        Ouint32 dtsValue = 0;

        if(block > 4){ //! 当前RK3568有5组GPIO（0--4）
            printf("Exceeds the current GPIO group number !! \n");
            return -1;
        }

        if(number > 31){ //! 每组GPIO最多32个（0--31）
            printf("Exceeds the current GPIO number !! \n");
            return -1;
        }

        Oint8* baseAddr = getMmapAddr(block);

        if(baseAddr == NULL){
            return -1;
        }

        if(number >= 16){
            number -= 16;
            baseAddr  += GPIO_SWPORT_DR_H_OFFSET;
        }else {
            baseAddr  += GPIO_SWPORT_DR_L_OFFSET;
        }

        //printf("test =====baseAddr===== 0x%x \n", baseAddr);

        //!! 取出原寄存器的数值；
        dtsValue = *(volatile Ouint32 *)baseAddr;
        //printf("test =====dtsValue1===== 0x%x \n", dtsValue);
        ioValue = (ioValue << number) | (ioValue << (number + 16));
        //printf("test =====dtsValue2===== 0x%x \n", ioValue);
        if(value){
            //!! GPIO输出高
            //!! 计算出当前GPIO对应的bit位
            dtsValue = dtsValue | ioValue ;
        }else{
            //!! GPIO输出底
            dtsValue = dtsValue & (~ioValue) ;
            ioValue = 1;
            ioValue = ioValue << (number + 16);
            dtsValue = dtsValue | ioValue ;
        }
        //printf("test =====dtsValue3===== 0x%x \n", dtsValue);
        *(volatile Ouint32 *)baseAddr = dtsValue;  

        
    }
#else
    Oint8 fpga_manage::setGpioHigLow(Ouint8 block, Ouint8 number, int value)
    {
        if ((block == 3) && (number == 1))  //flash_sel
        {
            flash_sel1_setlevel(value);            
        }
        else if ((block == 2) && (number == 30)) // cmd
        { 
            mcu_ctla_cmd1_setlevel(value);
        }
        else if ((block == 3) && (number == 10))  // fpga_program
        {
            fpga_program1_setlevel(value);
        }

        return 0;
        
    }
#endif


Ouint8 fpga_manage::fpga_ctl_int1_gpio_get(void)
{
    int fd;
    char buf[2];
    int ret;
    Ouint8 value;

    printf("fpga_ctl_int1_gpio_get\n");

    fd = open("/sys/devices/platform/gpioctrl/fpga2_ctl1_int1", O_RDWR);
    printf("gpio_fd: %d\n", fd);
    if (fd < 0)
    {
        perror("open fpga2_ctl_int1 error\n");
        close(fd);
        return fd;
    }
    printf("================================================================\n");
    ret = read(fd,buf,1);
    if (ret < 0)
    {
        perror("fpga_ctl_int1 read error\n");
    }
    printf("********************************\n");
    printf("gpio value is %s\n",buf);
    


    // unsigned int gpio_num = chip_info.base + 3;    

    close(fd);

    if(buf[0] =='0')
    {
        value = 0;
    }else{
        value =1;
    }

    return value;
}


/**
 * @brief fpga_manage::getGpioReadStatus
 * @param block 是哪一组GPIO
 * @param number 是当前组中的第几个gpio（A0-B0-C0-D0-D7分别对应32个GPIO）
 * @return 1:高电平 0:低电平 其他数值失败
 */
Oint8 fpga_manage::getGpioReadStatus(Ouint8 block, Ouint8 number)
{

    Ouint32 dtsValue = 0;

    if(block > 4){ //! 当前RK3568有5组GPIO（0--4）
        printf("Exceeds the current GPIO group number !! \n");
        return -1;
    }

    if(number > 31){ //! 每组GPIO最多32个（0--31）
        printf("Exceeds the current GPIO number !! \n");
        return -1;
    }

    Oint8* baseAddr = getMmapAddr(block);

    if(baseAddr == NULL){
        return -1;
    }

    baseAddr  += GPIO_EXT_PORT;


    //printf("test =====baseAddr===== 0x%x \n", baseAddr);

    //!! 取出原寄存器的数值；
    dtsValue = *(volatile Ouint32 *)baseAddr;

    dtsValue = (dtsValue >> number) & 0x00000001;

    return (Oint8)dtsValue;
}


//命令管理线程，用于处理命令
void * fpga_manage::fpgamanageThread(void * p_about_fpga_manage)
{
    if(!p_about_fpga_manage)
    {
        return NULL;
    }


    while(!g_AppExit)
    {
        //防止抢占CPU资源
        //if(g_fpga_c331_start){

        fpga_manage_deal(p_about_fpga_manage) ;

        //}

        // usleep(1000);
        sleep(1);
    }

    return NULL;
}


void fpga_manage::update_muc_file(char *sy_name, Ouint32 file_offset, Ouint32 file_len)
{
    //Ouint32 file_len;
    //Ouint32 file_offset;
    FILE* file_onbon;

    for(int s=0;s<5*1024*1024;s++){
        fileBuf_onbon[s] = 0x00;
    }

    Utils::_file_deal_mutex.lock();
    file_onbon = fopen(sy_name, "rb");
    if(file_onbon == NULL){
        Utils::_file_deal_mutex.unlock();
        system("sync") ;
        usleep(1000*100) ;
        return;
    }

    fseek(file_onbon,file_offset,SEEK_SET) ;
    fread((void *)fileBuf_onbon,1,file_len,file_onbon) ;
    fclose(file_onbon) ;
    Utils::_file_deal_mutex.unlock();



    Utils::_file_deal_mutex.lock();
    file_onbon = fopen("/data/app/ovpG32N2", "wb+");

    if(file_onbon == NULL){
        BX_printf("\n\n  error!!!! file_onbon N= NULL \n ") ;
        file_onbon = fopen("/data/app/ovpG32N2", "wb");
    }else{
        if(file_onbon == NULL){
            BX_printf("\n\n  error!!!! file_onbon N1= NULL \n ") ;
        }
    }

    fwrite((void *)fileBuf_onbon, file_len, 1, file_onbon );
    fclose(file_onbon) ;
    Utils::_file_deal_mutex.unlock();
    system("sync") ;
    usleep(1000*10) ;

    //read
    Ouint32 m,j,i=16;
    Ouint8 *p_data = new Ouint8[1024];
    Utils::_file_deal_mutex.lock();
    file_onbon = fopen("/data/app/ovpG32N2", "rb");
    for(m=0;m<file_len/1024;m++){
        fread(p_data, 1, 1024, file_onbon);
        for(j=0;j<1024;j++){
            if(p_data[j] != fileBuf_onbon[m*1024+j]){
                i = 15;
                BX_printf("\n read app found comare 01!!!!!! \n") ;
                fclose(file_onbon);
                Utils::_file_deal_mutex.unlock();
                break;
            }
        }
    }

    if(m==file_len/1024){
        for(j=0;j<file_len - m*1024;j++){
            fread(p_data, 1, file_len - m*1024, file_onbon);

            if(p_data[j] != fileBuf_onbon[m*1024+j]){
                i = 15;
                BX_printf("\n read app found comare 02!!!!!! \n") ;
                fclose(file_onbon);
                Utils::_file_deal_mutex.unlock();
                break;
            }
        }
    }

    if(i==16){
        fclose(file_onbon);
        Utils::_file_deal_mutex.unlock();
    }

    delete p_data;
    p_data = NULL ;
}


void fpga_manage::update_txc_file(char *sy_name, Ouint8 flashName, Ouint32 file_offset)
{
    //start to update the txc
    Ouint32 file_len;
    Ouint16	start_block;
    //uint16	offset=1;
    //Ouint8	erase_type;
    Ouint8	erase_times = 1;
    Ouint8  erase_mode = ERASE_4K;
    Ouint32 addr = 0;
    Ouint8 ver_year;
    Ouint8 ver_month;
    Ouint8 ver_date;
    Ouint8 ver_hard;
    Ouint32 m,j,i=16;
    FILE* file_onbon;
    //由于是FCG格式，所以需要再调整

    //write
    addr = 0;

    //FCG Header 31

    Utils::_file_deal_mutex.lock();
    file_onbon = fopen(sy_name, "rb");
    if(file_onbon == NULL){
        Utils::_file_deal_mutex.unlock();
        system("sync") ;
        usleep(1000*100) ;
        return;
    }

    fseek(file_onbon,file_offset,SEEK_SET) ;
    fread((void *)fileBuf_onbon,1,64,file_onbon) ;
    fclose(file_onbon) ;
    Utils::_file_deal_mutex.unlock();

    ver_year = fileBuf_onbon[23];
    ver_month = fileBuf_onbon[24];
    ver_date = fileBuf_onbon[25];
    ver_hard = fileBuf_onbon[26];


    BX_printf("\n file_type = %#x (1-FCG,2-ACG)\n", fileBuf_onbon[16] );
    BX_printf("\n file_version = %#x \n", fileBuf_onbon[17] );
    BX_printf("\n ControllerClass = %#x \n",SPLIT_8_to_16(fileBuf_onbon,18)) ;
    BX_printf("\n ControllerClcass = %#x (00-sending,1-rcv,2-mult)\n", fileBuf_onbon[20] );
    BX_printf("\n Version = %#x,%#x,%#x,%#x \n", ver_year,ver_month,ver_date,ver_hard);
    file_len = SPLIT_8_to_32_LITTLE(fileBuf_onbon,31);
    BX_printf("\n file_len = %#x \n", file_len);


    //sec
    for(addr = 0; addr < file_len ; ){
        start_block = addr/g_Global->FLASH_SEC_SIZE;
        BX_printf("\n erase = %d , addr = %d\n " , start_block, addr);
        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(flashName,start_block, erase_mode,erase_times) ;
        addr += g_Global->FLASH_SEC_SIZE;
        usleep(1000) ;
    }

    addr = 64;

    for(m=0;m<file_len/4096;m++){
        Utils::_file_deal_mutex.lock();
        file_onbon = fopen(sy_name, "rb");
        if(file_onbon == NULL){
            Utils::_file_deal_mutex.unlock();
            BX_printf("\n back error 000\n");
            system("sync") ;
            usleep(1000*100) ;
            return;
        }
        fseek(file_onbon,file_offset + addr + m*4096 ,SEEK_SET) ;
        fread((void *)(&fileBuf_onbon[4]), 1, 4096, file_onbon);
        fclose(file_onbon) ;
        Utils::_file_deal_mutex.unlock();
        //BX_printf("\n write addr = %#x\n " , addr);
        usleep(1000) ;

        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,m*4096,fileBuf_onbon,4096) ;

    }

    if(file_len%4096){
        Utils::_file_deal_mutex.lock();
        file_onbon = fopen(sy_name, "rb");
        if(file_onbon == NULL){
            Utils::_file_deal_mutex.unlock();
            system("sync") ;
            BX_printf("\n back error 002 \n");
            usleep(1000*100) ;
            return;
        }
        fseek(file_onbon,file_offset + addr + m*4096,SEEK_SET) ;
        fread((void *)(&fileBuf_onbon[4]), 1, file_len%4096, file_onbon);
        fclose(file_onbon) ;
        Utils::_file_deal_mutex.unlock();
        usleep(1000) ;

        fpga_manage::p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(flashName,m*4096,fileBuf_onbon,file_len%4096);
    }
    //ui->label_log->setText("downing over !!!!");
    BX_printf("\n write over !!!!!\n ");

}



void fpga_manage::usb_upgrade_main_deal(void)
{
    
}


void fpga_manage::get_usb_file_list_path(void)
{

}




void fpga_manage::fpga_manage_deal(void * p_about_fpga_manage)
{
    //Ouint16 len ;
    //check fpga ver

    //check deal by pc
#if 1

    P_ONBONFPGAMANAGETHIS->check_fpga_rst();
    if(onbonsource::p_onbon_source->init_s5p210_state[FPGA_MASTER_VBYONE1] == init_s5p210_end){
        P_ONBONFPGAMANAGETHIS->power_up_fpga_start(1,FPGA_MASTER_VBYONE1);
    }
    if(onbonsource::p_onbon_source->init_s5p210_state[FPGA_MASTER_VBYONE1] == init_s5p210_end){
        P_ONBONFPGAMANAGETHIS->power_up_check_fpga_status(FPGA_MASTER_VBYONE1);
    }



    if(onbonsource::p_onbon_source->init_s5p210_state[FPGA_MASTER_VBYONE1] == init_s5p210_end){
        P_ONBONFPGAMANAGETHIS->reg_IRQ_Dealwith(FPGA_MASTER_VBYONE1,0);
    }

    if(onbonsource::p_onbon_source->init_s5p210_state[FPGA_MASTER_VBYONE1] == init_s5p210_end){
        // P_ONBONFPGAMANAGETHIS->Search_Card_Cmd();
        P_ONBONFPGAMANAGETHIS->Check_search_card();
    }


#else
    P_ONBONFPGAMANAGETHIS->power_up_fpga_start(1,FPGA_MASTER_VBYONE1);
#endif
}

#if 0

#else
Ouint32 fpga_manage::fpga_cmd_to_spi_data(Ouint32 ram_flash_sel, Ouint32 ram_addr, Ouint32 start_addr, Ouint32 wr_rd)
{

    Ouint32 temp_cmd;
    //清零
    temp_cmd = 0;
    //获取片选
    ram_flash_sel = ram_flash_sel & 0x0F;
    temp_cmd      = (temp_cmd | (ram_flash_sel << 1));

    //获取地址
    ram_addr = ram_addr & 0xff;
    temp_cmd   = (temp_cmd | (ram_addr << 8));

    start_addr = start_addr & 0x0FFF;
    temp_cmd   = (temp_cmd | (start_addr << 16));

    //读写方向
    wr_rd = wr_rd & 0x01;
    temp_cmd  = temp_cmd | wr_rd;

    return temp_cmd;
}
#endif


//
//for register
#if 1
Ouint32 fpga_manage::fpga_reg_cmd_to_spi_data(Ouint32 ram_flash_sel, Ouint32 ram_addr, Ouint32 start_addr, Ouint32 wr_rd, Ouint32 data)
{

    Ouint32 temp_cmd;

    //清零
    temp_cmd = 0;
    //获取片选
    ram_flash_sel = ram_flash_sel & 0x0F;
    temp_cmd      = (temp_cmd | (ram_flash_sel << 1));

    //获取地址
    ram_addr = ram_addr & 0xff;
    temp_cmd   = (temp_cmd | (ram_addr << 8));

    //FPGA会判断读写，读写寄存器这里直接置1
    start_addr = start_addr & 0x00FF;
    if(wr_rd == 0){
        start_addr |= ((data & 0xFF) << 8);
    }
    temp_cmd   = (temp_cmd | (start_addr << 16));

    //读写方向
    wr_rd = wr_rd & 0x01;
    temp_cmd  = temp_cmd | wr_rd;

    return temp_cmd;
}

#endif





void fpga_manage::read_fpga_register(Ouint32 reg, Ouint8 *value,Ouint8 sel_fpag)
{
    //特别提醒 在与FPGA通讯时[H4D后级时 千万不允许修改模拟通讯的宏MSPI_FPGA1_MOSI_H]
#ifdef OUTPUT_LEDNET

    Ouint8 cmd_buf[4],i;
    Ouint8 buf[2];
    Ouint32 fpga_cmd;
    int fd ;

    //使能命名功能
    Utils::_spi_mutex.lock();
    setGpioHigLow(2, 30, 1);
    // usleep(10000);

    fd = fpga_vbyone1_fd ;
    //命令值
    fpga_cmd = fpga_reg_cmd_to_spi_data(FPGA_CMD_SEL_REG, 0, reg , FPGA_CMD_EN_RD,0XFF);

    cmd_buf[3] = (fpga_cmd >> 24) & 0x0FF;
    cmd_buf[2] = (fpga_cmd >> 16) & 0x0FF;
    cmd_buf[1] = (fpga_cmd >> 8) & 0x0FF;
    cmd_buf[0] = fpga_cmd & 0x0FF;

    //写命令到FPGA
    //spi_write_nbyte(cmd_buf, 2);

    p_fpga_drv->SPI_Transfer_Write(fd ,&cmd_buf[0] , 4) ;

    //写对应数据
    setGpioHigLow(2, 30, 0);
    // usleep(10000);
    //读数据，1个字节一写
    cmd_buf[0] = 0xff ;
    buf[0]=0x00;
    p_fpga_drv->SPI_Transfer(fd ,cmd_buf , buf ,1) ;
    //p_fpga_drv->SPI_Read(fd ,buf, 1) ;

    Utils::_spi_mutex.unlock();
    *value = buf[0] & 0xFF;

#endif

}


void fpga_manage::write_fpga_register(Ouint32 reg, Ouint8 value, Ouint8 sel_fpag ,Ouint8 reg_mask)
{
#if 1
    //特别提醒 在与FPGA通讯时[H4D后级时 千万不允许修改模拟通讯的宏MSPI_FPGA1_MOSI_H]
#ifdef OUTPUT_LEDNET
    Ouint8 cmd_buf[4];
    Ouint8 buf[2]/*,i*/;
    Ouint32 fpga_cmd;
    int fd ;

    //使能命名功能
    Utils::_spi_mutex.lock();

    setGpioHigLow(2, 30, 1);
    // usleep(10000);
    fd = fpga_vbyone1_fd ;
    //命令值
    fpga_cmd = fpga_reg_cmd_to_spi_data(FPGA_CMD_SEL_REG, 0, reg , FPGA_CMD_EN_WR , reg_mask);

    cmd_buf[3] = (fpga_cmd >> 24) & 0x0FF;
    cmd_buf[2] = (fpga_cmd >> 16) & 0x0FF;
    cmd_buf[1] = (fpga_cmd >> 8) & 0x0FF;
    cmd_buf[0] = fpga_cmd & 0x0FF;
    //写命令到FPGA
    //spi_write_nbyte(cmd_buf, 2);

    p_fpga_drv->SPI_Transfer_Write(fd ,&cmd_buf[0] , 4) ;

    //写对应数据
    setGpioHigLow(2, 30, 0);
    // usleep(10000);
    //写数据，2个字节一写
    buf[0] = value;
    //spi_write_nbyte(buf, 1);
    p_fpga_drv->SPI_Transfer_Write(fd ,buf , 1) ;

    Utils::_spi_mutex.unlock();

#endif
#endif
}




void fpga_manage::write_LCD_register(Ouint32 reg, Ouint8 *value, Ouint8 sel_fpag ,Ouint8 num_len )
{
#if 1
    //特别提醒 在与FPGA通讯时[H4D后级时 千万不允许修改模拟通讯的宏MSPI_FPGA1_MOSI_H]
#ifdef OUTPUT_LEDNET
    int fd ;

    //使能命名功能
    Utils::_spi_mutex.lock();
    if(sel_fpag==FPGA_MASTER_VBYONE1){

        setGpioHigLow(2, 30, 1);
        fd = fpga_vbyone1_fd ;
    }

    if(sel_fpag==FPGA_MASTER_VBYONE1){
        setGpioHigLow(2, 30, 0);
    }

    p_fpga_drv->SPI_Transfer_Write(fd ,(unsigned char *)&reg , 1) ;
    for(int i=0;i<num_len;i++){
        p_fpga_drv->SPI_Transfer_Write(fd ,&value[i] , 1) ;
    }



    Utils::_spi_mutex.unlock();

#endif
#endif
}



/*!
*  @brief	Brightness_task_run 自动调亮任务
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Search_Card_task_run(void)
{

    //处理FPGA中断
    reg_IRQ_Dealwith(FPGA_MASTER_VBYONE1,0);
    //再检查网口缓存区数据
    //Check_eth_CMD_cache();
    //接收命令处理
    //    Search_CMD_back_result();

}

/*!
*  @brief	Brightness_task_run 自动调亮任务
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_task_run(void)
{

    //处理FPGA中断
    reg_IRQ_Dealwith(FPGA_MASTER_VBYONE1,0);
    //再检查网口缓存区数据
    //Check_eth_CMD_cache();
    //接收命令处理setGpioHigLow
    //    Mcu_CMD_back_result();

}

/*!
 *  @brief	Power_ctrl_init()  ---初始化用到的全局变量
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_ctrl_init(void)
{
    g_power_ctrl_flag = 0;                //!<表示MCU曾控制过，0表示由外部操作引起的变化不做处理
    g_power_ticks_flag = 0;               //!<计时标志，0表示需要计时时重新开始计时
    g_power_open_running = 0;             //!<1表示正在开启中，可能会被打断
    g_power_close_running = 0;            //!<1表示正在关闭中，可能会被打断
    g_first_start_flag = 0;               //!<0表示刚上电，对于此时的状态可不做处理
    g_signal_state = 0;
    g_power_io_num = 1;                   //!<继电器编号，从1开始
    g_power_port_num = 0;
    g_power_sel_fpga = 0;
    //g_check_eth_ticks = 0;                //!<FPGA网口空闲检查计时
    g_change.sys_Power_ctrl_enable = 0;   //!<1表示多功能卡打开无信号关闭电源功能
    g_change.sys_power_check_time = 0;    //!<多功能卡检查计时
    g_change.sys_power_send_time = 0;     //!<多条命令发送时的间隔时间
    g_change.sys_power_delay_time = 0;    //!<从无信号到发送关闭命令间的延时
    g_change.sys_signal_check_time = 0;
}

/*!
 *  @brief	Power_ctrl_reset()  ---重置用到的全局变量
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_ctrl_reset(void)
{
    g_power_ticks_flag = 0;
    g_first_start_flag = 1;
    g_power_io_num = 1;
    g_change.sys_Power_ctrl_enable = 0;
    g_change.sys_power_check_time = 0;
    g_change.sys_power_send_time = 0;
    g_change.sys_power_delay_time = 0;

}

/*!
 *  @brief	Send_write_VMF_reg_cmd 发送写VMF的寄存器数据的命令
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Send_write_VMF_reg_cmd(OPTION option,Ouint8 io_num)
{
    Ouint8 crc_xor,n,data/*,port_num*/;
    Ouint8 reg_addr,reg_mask,reg_data;
    Ouint16 data_len,length;
    Ouint8 SEND_WRITE_VMF_REG_CMD[15];
    /*PHY_HEAD *msg;

    msg = (PHY_HEAD *)SEND_WRITE_VMF_REG_CMD;

    msg->DstAddr = g_change.sys_VMF_port;
    msg->SrcAddr = FPGA_DEFAULT_ADDR;
    msg->ProtocolVersion = 0x10;
    msg->SequenceNumber = 0xBB;
    msg->ControllerClass = 0x03;
    msg->Reserved0 = 0;
    msg->Reserved1 = 0;*/

    SEND_WRITE_VMF_REG_CMD[0] = g_change.sys_VMF_port & 0xff;
    SEND_WRITE_VMF_REG_CMD[1] = (g_change.sys_VMF_port>>8) & 0xff;
    SEND_WRITE_VMF_REG_CMD[2] = FPGA_DEFAULT_ADDR & 0xff;
    SEND_WRITE_VMF_REG_CMD[3] = (FPGA_DEFAULT_ADDR>>8) & 0xff;
    SEND_WRITE_VMF_REG_CMD[4] = 0x10;
    SEND_WRITE_VMF_REG_CMD[5] = 0xBB;
    SEND_WRITE_VMF_REG_CMD[6] = 0x03;
    SEND_WRITE_VMF_REG_CMD[7] = 0x00;
    SEND_WRITE_VMF_REG_CMD[8] = 0x00;


    data = (option == OPEN ? 0x03 : 0x01);
    if((io_num > 0) && (io_num <= 4)){
        n = io_num - 1;
        reg_addr = 0x02;
        reg_mask = 0x03 << (n * 2);
        reg_data = data << (n * 2);
    }else if((io_num > 4) && (io_num <= 8)){
        n = io_num - 5;
        reg_addr = 0x03;
        reg_mask = 0x03 << (n * 2);
        reg_data = data << (n * 2);
    }else{
        return;
    }

    /*msg->Frame_data[0] = CMD_REGISTER_WRITE;
    msg->Frame_data[1] = reg_addr;
    msg->Frame_data[2] = reg_mask;
    msg->Frame_data[3] = 0;
    msg->Frame_data[4] = reg_data;*/

    SEND_WRITE_VMF_REG_CMD[9] = CMD_REGISTER_WRITE;
    SEND_WRITE_VMF_REG_CMD[10] = reg_addr;
    SEND_WRITE_VMF_REG_CMD[11] = reg_mask;
    SEND_WRITE_VMF_REG_CMD[12] = 0;
    SEND_WRITE_VMF_REG_CMD[13] = reg_data;


    data_len = 15;//!<9+5+1
    length = data_len - 1;//去掉校验位
    //crc_xor = CalcXOR((uint8 *)SEND_WRITE_VMF_REG_CMD,length);
    crc_xor = Utils::BCC((Ouint8 *)SEND_WRITE_VMF_REG_CMD,length);
    //msg->Frame_data[5] = v_xor;
    SEND_WRITE_VMF_REG_CMD[14] = crc_xor;



    Send_to_port(SEND_WRITE_VMF_REG_CMD,data_len,g_power_port_num,g_power_sel_fpga);
}

/*!
 *  @brief	VMF_reg_back_result 处理VMF返回结果
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::VMF_reg_back_result(Ouint8 sel_fpga)
{
    //PHY_HEAD *msg;
    PhyData_Type *msg;
    //PHY_RX *phy_rx;
    Ouint8 phy_rx[RAM_MAX_LEN];
    Ouint8 crc_xor,rcv_xor;
    //uint16 n;
    Ouint32 eth_data_len=1;

    switch (g_power_port_num) {
    case 0:
    case 1:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_12,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_12] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0x03) << 8)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_12,sel_fpga);
        break;
    case 2:
    case 3:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_34,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_34] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0x0c) << 6)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_34,sel_fpga);
        break;
    case 4:
    case 5:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_56,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_56] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0x30) << 4)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_56,sel_fpga);
        break;
    case 6:
    case 7:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_78,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_78] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0xc0) << 2)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_78,sel_fpga);
        break;
    case 8:
    case 9:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_910,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_910] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0x03) << 8)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_910,sel_fpga);
        break;
    case 10:
    case 11:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_1112,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_1112] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0x0c) << 6)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1112,sel_fpga);
        break;
    case 12:
    case 13:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_1314,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_1314] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0x30) << 4)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1314,sel_fpga);
        break;
    case 14:
    case 15:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_1516,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_1516] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0xc0) << 2)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1516,sel_fpga);
        break;
    default:
        break;
    }

    //默认从机模式
    //if(phy_rx->rcv_flag == PHY_GF_VALID){
    if(VMF_port_data_valid){
        //帧解析
        //msg = (PHY_HEAD *)phy_rx->data;
        msg = (PhyData_Type *)phy_rx;
        //!<计算除最后一位校验位以外的XOR值
        //crc_xor = CalcXOR((Ouint8 *)phy_rx->data, phy_rx->rcv_len - 1);
        crc_xor = Utils::BCC(phy_rx, eth_data_len - 1);
        //!<接收的XOR校验值
        rcv_xor = phy_rx[eth_data_len - 1];
        if(rcv_xor == crc_xor){
            //命令帧被处理
            //!<返回接收到的数据
            //检查命令返回结果是否执行成功
            //if((msg->Frame_data[0] == g_change.sys_send_cmd_value)&&(msg->Frame_data[1] == 0x00)){
            if((msg->cmd == g_change.sys_send_cmd_value)&&(msg->data[0] == 0x00)){
                //命令返回执行成功
                g_change.sys_VMF_data_valid = 1;
                g_change.sys_send_cmd_result = 1;
                //g_power_io_num++;
            }
            else{
                //命令执行异常需要重发
                g_change.sys_send_cmd_result = 2;
            }

        }else{
            //!<帧出错
            MCU_REG_func[sel_fpga][0x55] = MCU_REG_func[sel_fpga][0x55] + 1;

            //命令执行异常需要重发
            g_change.sys_search_result = 2;
        }

        //phy_rx->rcv_flag = PHY_GF_INVALID;
        VMF_port_data_valid = 0;
    }
}

/*!
 *  @brief	wait_VMF_result  ---等待多功能卡回复
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::wait_VMF_result(void)
{
    Ouint32 run_flag;
    Ouint32 run_state;
    Ouint32 time_delay;

    ////是否有无多功能卡
    if(g_change.sys_VMF_port > 0){
        run_flag = 1;
    }
    else{
        run_flag = 0;
    }

    //默认起始状态
    run_state = 0;

    while(run_flag){


        //循环进入不同的状态
        switch(run_state){
        case 0:{
            ////获取当前时间值
            time_delay = G_timeTicks;

            g_change.sys_send_cmd_result = 0;
            //RAM读命令
            g_change.sys_send_cmd_value = 0xA0;
            //数据先无效
            g_change.sys_VMF_data_valid = 0;

            run_state = 1;
            break;
        }
        case 1:{
            //等待VMF数据收到
            //处理FPGA中断
            reg_IRQ_Dealwith(g_power_sel_fpga,0);
            //接收命令处理
            VMF_reg_back_result(g_power_sel_fpga);
            if((g_change.sys_send_cmd_result != 0)||((G_timeTicks - time_delay) >= 35)){

                if(g_change.sys_send_cmd_result == 0){
                    //                        BX_printf("\n vmf REG message back error!!!,value:%d\n",g_change.sys_send_cmd_result);
                }

                //退出当前循环
                run_flag = 0;
                run_state = 0;
            }


            break;
        }
        default:{

            run_flag = 0;
        }

        }

    }

}

void fpga_manage::eth_data_send_stop(void)
{
    if(g_power_io_num > 8){
        g_power_ctrl_flag = 1;
        g_power_close_running = 0;//!<关闭继电器过程中未被打断
        g_power_io_num = 1;

        //    BX_printf("\npower close done!!\n");

        return;
    }

    if(G_timeTicks - g_change.sys_power_send_time > VMF_SEND_DELAY){
        Send_write_VMF_reg_cmd(CLOSE,g_power_io_num);
        wait_VMF_result();
        g_change.sys_power_send_time = G_timeTicks;
        g_power_io_num++;
    }

}

void fpga_manage::eth_data_send_start(void)
{
    if(g_power_io_num > 8){
        g_power_ctrl_flag = 0;
        g_power_open_running = 0;//!<开启过程中未被打断
        g_power_io_num = 1;

        //    BX_printf("\npower open done!!\n");

        return;
    }

    if(G_timeTicks - g_change.sys_power_send_time > VMF_SEND_DELAY){
        Send_write_VMF_reg_cmd(OPEN,g_power_io_num);
        wait_VMF_result();
        g_change.sys_power_send_time = G_timeTicks;
        g_power_io_num++;
    }

}

/*!
 *  @brief	Power_check_VMF()  ---检查多功能卡
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_check_VMF(void)
{
    Ouint8 port_num;

    ////查找是否有无多功能卡，默认优先使用网口1上的多功能卡
    if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH0_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH1_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH2_VMF] > 0){
        ////只读取第三个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH3_VMF] > 0){
        ////只读取第四个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH4_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH5_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH6_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH7_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH8_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH9_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH10_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH11_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH12_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH13_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH14_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH15_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }
#if (defined OUTPUT_BOARD_2)
    else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH0_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH1_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH2_VMF] > 0){
        ////只读取第三个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH3_VMF] > 0){
        ////只读取第四个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH4_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH5_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH6_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH7_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH8_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH9_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH10_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH11_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH12_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH13_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH14_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH15_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }
#endif
    else{
        //BX_printf("\nnot find vmf card!!!\n");
        g_change.sys_VMF_port = 0x00;
        g_change.sys_VMF_group = 0;
    }



    switch(g_change.sys_VMF_port){
    case SP_P1_VMF_ADDR:
        port_num = 0;
        break;
    case SP_P2_VMF_ADDR:
        port_num = 1;
        break;
    case SP_P3_VMF_ADDR:
        port_num = 2;
        break;
    case SP_P4_VMF_ADDR:
        port_num = 3;
        break;
    default:
        port_num = 0;
        break;
    }

    //if(g_change.sys_VMF_group != 1){//第二组属于后四个网口
    g_power_port_num = port_num + (g_change.sys_VMF_group - 1) * 4;

    if(g_change.sys_VMF_group < 5){
        g_power_sel_fpga = FPGA_MASTER_VBYONE1;
    }else{
#if (defined OUTPUT_BOARD_2)
        g_power_sel_fpga = FPGA_MASTER_VBYONE2;
        g_power_port_num -= 16;
#endif
    }
    //}



    //    BX_printf("vmf_addr:0x%x port_num:%d sel_fpga:%d\n",g_change.sys_VMF_port,g_power_port_num,g_power_sel_fpga);
}

/*!
 *  @brief	Send_read_VMF_RAM0_data_cmd 发送读取VMF的RAM0区数据的命令
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Send_read_VMF_RAM0_data_cmd(void)
{
    Ouint8 crc_xor;;
    Ouint8 data_len;

    SEND_READ_VMF_RAM0_CMD[0] = g_change.sys_VMF_port & 0xFF;
    SEND_READ_VMF_RAM0_CMD[1] = (g_change.sys_VMF_port >> 8) & 0xFF;

    //crc_xor = CalcXOR((Ouint8 *)SEND_READ_VMF_RAM0_CMD, 18);
    crc_xor = Utils::BCC((Ouint8 *)SEND_READ_VMF_RAM0_CMD, 18);
    SEND_READ_VMF_RAM0_CMD[18] = crc_xor;//设置最后一位校验码

    data_len = 19 ;//- 1;
    Send_to_port(SEND_READ_VMF_RAM0_CMD,data_len,g_power_port_num,g_power_sel_fpga);


}

/*!
 *  @brief	VMF_RAM0_data_back_result 处理VMF返回结果
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::VMF_RAM0_data_back_result(Ouint8 sel_fpga)
{
    //PHY_HEAD *msg;
    PhyData_Type *msg;
    //PHY_RX *phy_rx;
    Ouint8 phy_rx[RAM_MAX_LEN];
    Ouint8 crc_xor,rcv_xor;
    Ouint16 n;
    Ouint32 eth_data_len = 2;

    switch (g_power_port_num) {
    case 0:
    case 1:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_12,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_12] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0x03) << 8)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_12,sel_fpga);
        break;
    case 2:
    case 3:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_34,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_34] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0x0c) << 6)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_34,sel_fpga);
        break;
    case 4:
    case 5:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_56,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_56] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0x30) << 4)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_56,sel_fpga);
        break;
    case 6:
    case 7:
        read_from_register(RX_RAM_HIGH_REG,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_78,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_78] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG] & 0xc0) << 2)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_78,sel_fpga);
        break;
    case 8:
    case 9:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_910,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_910] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0x03) << 8)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_910,sel_fpga);
        break;
    case 10:
    case 11:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_1112,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_1112] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0x0c) << 6)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1112,sel_fpga);
        break;
    case 12:
    case 13:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_1314,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_1314] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0x30) << 4)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1314,sel_fpga);
        break;
    case 14:
    case 15:
        read_from_register(RX_RAM_HIGH_REG2,sel_fpga);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_1516,sel_fpga);
        eth_data_len = (MCU_REG_func[sel_fpga][RX_RAM_LOW_REG_1516] | ((MCU_REG_func[sel_fpga][RX_RAM_HIGH_REG2] & 0xc0) << 2)) + 1;
        read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1516,sel_fpga);
        break;
    default:
        break;
    }

    //默认从机模式
    //if(phy_rx->rcv_flag == PHY_GF_VALID){
    if(VMF_port_data_valid){
        //帧解析
        //msg = (PHY_HEAD *)phy_rx->data;
        msg = (PhyData_Type *)phy_rx;
        //!<计算除最后一位校验位以外的XOR值
        //crc_xor = CalcXOR((Ouint8 *)phy_rx->data, phy_rx->rcv_len - 1);
        crc_xor = Utils::BCC(phy_rx, eth_data_len - 1);
        //!<接收的XOR校验值
        rcv_xor = phy_rx[eth_data_len - 1];
        if(rcv_xor == crc_xor){
            //命令帧被处理
            //!<返回接收到的数据
            //检查命令返回结果是否执行成功
            //if((msg->Frame_data[0] == g_change.sys_send_cmd_value)&&(msg->Frame_data[1] == 0x00)){
            if((msg->cmd == g_change.sys_send_cmd_value)&&(msg->data[0] == 0x00)){
                //命令返回执行成功
                g_change.sys_VMF_data_valid = 1;
                g_change.sys_send_cmd_result = 1;

                //读取VMF返回的256个字节数据
                for(n = 0; n < 0x100; n++){
                    G_VMF_RAM0_VALUE[n] = msg->data[1 + n];
                }

            }
            else{
                //命令执行异常需要重发
                g_change.sys_send_cmd_result = 2;
            }

        }else{
            //!<帧出错
            MCU_REG_func[sel_fpga][0x55] = MCU_REG_func[sel_fpga][0x55] + 1;

            //命令执行异常需要重发
            g_change.sys_search_result = 2;
        }
        //MCU_CMD_RX_flag.cmd_valid = 0;
        //phy_rx->rcv_flag = PHY_GF_INVALID;
        VMF_port_data_valid = 0;
    }
}

/*!
 *  @brief	Brightness_VMF_run 等待VMF返回命令
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_VMF_run(void)
{

    //处理FPGA中断
    reg_IRQ_Dealwith(g_power_sel_fpga,0);
    //接收命令处理
    VMF_RAM0_data_back_result(g_power_sel_fpga);

}

/*!
 *  @brief	Power_read_VMF_value()  ---检查多功能卡
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_read_VMF_value(void)
{
    Ouint32 run_flag;
    Ouint32 run_state;
    Ouint32 time_delay;

    ////是否有无多功能卡
    if(g_change.sys_VMF_port > 0){
        run_flag = 1;
    }
    else{
        run_flag = 0;
    }

    //默认起始状态
    run_state = 0;

    while(run_flag){


        //循环进入不同的状态
        switch(run_state){
        case 0:{
            //读取VMF卡的RAM0区数据
            Send_read_VMF_RAM0_data_cmd();
            ////获取当前时间值
            time_delay = G_timeTicks;

            g_change.sys_send_cmd_result = 0;
            //RAM读命令
            g_change.sys_send_cmd_value = 0x61;
            //数据先无效
            g_change.sys_VMF_data_valid = 0;

            run_state = 1;
            break;
        }
        case 1:{
            //等待VMF数据收到
            Power_VMF_run();
            if((g_change.sys_send_cmd_result != 0)||((G_timeTicks - time_delay) >= 35)){

                if(g_change.sys_send_cmd_result == 0){
                    //                        BX_printf("\nvmf RAM message back error!!!,value:%d\n",g_change.sys_send_cmd_result);
                }else{
                    //                        BX_printf("\nvmf RAM message back OK!!!\n");
                }


                //退出当前循环
                run_flag = 0;
                run_state = 0;
            }


            break;
        }
        default:{

            run_flag = 0;
        }

        }

    }

}

/*!
 *  @brief	Power_ctrl_filter()  ---- 电源控制抗干扰处理
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_ctrl_filter(void)
{

    ////VMF的数值表有更新
    if(g_change.sys_VMF_data_valid){

        ////如果电源控制打开的话
        if(G_VMF_RAM0_VALUE[0x2C] == 0x01){
            g_change.sys_Power_ctrl_enable = 1;
            //           BX_printf("\nvmf power ctrl enable!!!\n");
        }else{
            g_change.sys_Power_ctrl_enable = 0;
            //           BX_printf("\nvmf power ctrl not enable!!!\n");
        }

        //写入到寄存器区
        MCU_REG_func[g_power_sel_fpga][0x43] = g_change.sys_Power_ctrl_enable;
        g_change.sys_VMF_data_valid = 0;
    }


}

/*!
 *  @brief	Power_ctrl_task()
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_ctrl_task(void)
{
    Power_check_VMF();//检查是否有多功能卡
    Power_read_VMF_value();//从多功能卡获取配置参数
    Power_ctrl_filter();//电源控制数据过滤
}

/*!
 *  @brief	Power_ctrl_deal()
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Power_ctrl_deal(void)
{

}

/*!
* @brief   judge_card_state
* 搜索卡命令
* @param 	要查询的网口(master)
* @return	网口状态 0:未连接 1:已连接
* @note
*/
#if 0
Ouint8 fpga_manage::judge_card_state(uint32 port,uint32 *port1)
{
    Ouint8 temp,data,i;
    //Ouint8 flag = 0 ;

    data = MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];//!<获取当前全部网口连接状态

    //查找当前有效的端口
    for(i=port;i<DEVICE_OUT_NUM;i++){
        temp = (data >> i)&0x01;
        //当前网口有卡连接
        if(temp){
            *port1 = i;
            return temp;
        }
    }

    //查找当前有效的端口
    for(i=0;i<port;i++){
        temp = (data >> i)&0x01;
        //当前网口有卡连接
        if(temp){
            *port1 = i;
            return temp;
        }
    }

    temp = (data >> port)&0x01;

    *port1 = port;
    return temp;
}
#endif


/*!
*  @brief	Brightness_save_rcv() 调亮值保存到接收卡
*  @param	none
*  @return	none
*  @note	none
*/
#if 0
void fpga_manage::Brightness_save_rcv(void)
{
    //是由于PC进行设置的  要求全部在线网口可以直接保存
    //Ouint8 xor;crc_xor,n,data,port_num
    Ouint8 data;
    uint32 port_value = 0,port_value1=0 ;

    //获得同步亮度处理时间
    //开始成功
    g_change.sys_Bri_result = 0;

    g_change.sys_hand_Bri_state = 0;
    g_change.sys_hand_Bri_flag = 1;

    data = MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG]; //& 0x0C;

    while(g_change.sys_hand_Bri_flag){

        switch(g_change.sys_hand_Bri_state){
        case 0:{
            //检测从卡是否存在，
            // if(((g_change.sys_FPGA_line_state & 0x0F) == 0x08) &&(g_change.sys_VSE_master_flag == 1)){
            //如果有从卡存在则发送到从卡上
            //    g_change.sys_hand_Bri_state = 1;
            // }
            // else{

            //是否存在卡连接
            if(data == 0x00){

                //命令执行完毕退出来
                g_change.sys_hand_Bri_flag = 0;
            }
            else{
                //直接进行两个网口发送

                data = judge_card_state(port_value1,&port_value1);
                port_value = port_value1;
                if(data){
                    g_change.sys_hand_Bri_flag = 0;
                }else{
                    g_change.sys_hand_Bri_state = 2;
                }
            }
            //}

            break;
        }
#if 0
            //由于M1X 不存在从卡问题 暂时放弃调试
        case 1:{
            ////分发数据给从卡，并保存到接收卡上
            Send_BRI_data_to_slave_txc_save();
            ////开始自身网口发送
            //是否存在卡连接
            if(data == 0x00){

                //命令执行完毕退出来
                g_change.sys_hand_Bri_flag = 0;
            }
            else{
                //直接进行两个网口发送
                g_change.sys_hand_Bri_state = 2;
            }
            break;
        }
#endif
        case 2:{
            //网口1开始,命令帧方式调亮
            //g_change.sys_search_port_flag = 0;//g_change.sys_hand_Bri_port_flag

            if(data == 0){
                //表示当前无网口 一般情况下 不会执行
                if(port_value1 >= (DEVICE_OUT_NUM)){//!<查到最后一个网口，重回第一个
                    port_value1 = 0;
                }else{
                    port_value1++;
                }
            }else{

                //Send_save_para_to_rcv(data);
                SEND_BRI_SAVE_CMD[2]=data;
                Send_rcv_card_cmd(port_value1,3,FPGA_MASTER_VBYONE1);
                Send_rcv_card_cmd(port_value1,3,FPGA_MASTER_VBYONE2);
                //缓存写RAM命令
                g_change.sys_send_cmd_value = 0x81;
                //开始结果默认失败
                g_change.sys_send_cmd_result = 0;
                //启动超时等待
                g_change.sys_hand_Bri_time = G_timeTicks;
                //
                if(g_change.sys_port0_rcv_num > 0){
                    g_change.sys_hand_Bri_save_time  = 25 + g_change.sys_port0_rcv_num;
                }
                else{
                    g_change.sys_hand_Bri_save_time  = 25 + g_change.sys_port1_rcv_num;
                }
                //跳转到状态3
                g_change.sys_hand_Bri_state = 3;
            }


            break;
        }
        case 3:{
            //循环查询命令是否执行成功
            Brightness_task_run();
            //等待命令执行结果
            if((g_change.sys_send_cmd_result == 1)||((G_timeTicks - g_change.sys_hand_Bri_time) >= g_change.sys_hand_Bri_save_time)){
                //命令执行是否错误
                if(g_change.sys_send_cmd_result != 1){
                    g_change.sys_Bri_result = 1;
                }

                /*if(data == 0x0C){
                    Send_save_para_to_rcv(data);
                    //缓存写RAM命令
                    g_change.sys_send_cmd_value = 0x81;
                    //开始结果默认失败
                    g_change.sys_send_cmd_result = 0;
                    g_change.sys_hand_Bri_time = G_timeTicks;
                    g_change.sys_hand_Bri_save_time  = 25 + g_change.sys_port1_rcv_num;
                    //跳转到状态3
                    g_change.sys_hand_Bri_state = 4;
                }
                    else{*/
                //Send_rcv_card_cmd(data,g_change.sys_hand_Bri_port_flag,2);

                g_change.sys_send_cmd_value = 0x81;
                //开始结果默认失败
                g_change.sys_send_cmd_result = 0;
                g_change.sys_hand_Bri_time = G_timeTicks;
                g_change.sys_hand_Bri_save_time  = 25 + g_change.sys_port1_rcv_num;
                //命令执行完毕退出来
                //g_change.sys_hand_Bri_flag = 0;

                //对端口进行检测
                if(port_value1 >= (DEVICE_OUT_NUM)){//!<查到最后一个网口，重回第一个
                    port_value1 = 0;
                }else{
                    port_value1++;
                }
                //查找下一个有效的
                data = judge_card_state(port_value1,&port_value1);

                if(port_value1 <= port_value){
                    //结束
                    g_change.sys_hand_Bri_flag = 0;
                }

                //}

            }

            break;
        }
#if 0
        case 4:{
            //循环查询命令是否执行成功
            Brightness_task_run();
            //等待命令执行结果
            if((g_change.sys_send_cmd_result == 1)||((G_timeTicks - g_change.sys_hand_Bri_time) >= g_change.sys_hand_Bri_save_time)){

                //命令执行是否错误
                if(g_change.sys_send_cmd_result != 1){
                    g_change.sys_Bri_result = 1;
                }
                //命令执行完毕退出来
                g_change.sys_hand_Bri_flag = 0;
            }

            break;
        }
#endif
        default:{
            //跳转到状态3
            g_change.sys_hand_Bri_flag = 0;
        }

        }

    }

}
#endif



/*!
*  @brief	Brightness_hand_dealwith() 手动调亮时运行的状态机
*  @param	type 0表示强制初始化各个网口 1表示单独处理一个
*  @return	none
*  @note	由于单个网口的方式 会使调节网口亮度时不同步
*/
int fpga_manage::Brightness_hand_dealwith(Ouint8 type)
{
  
    return 0;
}


/*!
*  @brief	Brightness_hand_dealwith() 手动调亮时运行的状态机
*  @param	type 0表示强制初始化各个网口 1表示单独处理一个
*  @return	none
*  @note	由于单个网口的方式 会使调节网口亮度时不同步
*/
int fpga_manage::Brightness_message_dealwith(Ouint8 value)
{
    Ouint8 cmd_value=1;
    Ouint16 data[2]={0};
    Ouint16 val;

    Ouint8 com_result = 0 ;

    //获得同步亮度处理时间
    //开始成功
    g_change.sys_Bri_result = 0;

    g_change.sys_hand_Bri_state = 0;
    g_change.sys_hand_Bri_flag = 1;


    data[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
    // BX_printf("\n===================Brightness_message_dealwith=================data=%d\n",data[0]);

    while(g_change.sys_hand_Bri_flag){

        switch(g_change.sys_hand_Bri_state){
            case 0:{
                //是否存在卡连接
                if((data[0] == 0x00) ){
                    //命令执行完毕退出来
                    g_change.sys_hand_Bri_flag = 0;
                    com_result = 1;
                }
                else{
                    //直接进行两个网口发送
                    g_change.sys_hand_Bri_state = 2;
                    //turn=0;
                    cmd_value=1;
                }
                break;
            }
            case 2:{

                //使能同步帧发送亮度值 [主FPGA参数即可]
//                if(MCU_RAM_PARA[0x100] == 0x01){
                MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x100] = 0x01;
                if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x100] == 0x01){
                    //启动硬件调亮(0x03寄存器BIT3直接就是1，不再进行判断)
                    //if(MCU_REG_func[FPGA_MASTER_VBYONE1][0x03] & 0x08){
                
                    //拷贝命令
                    // BX_printf("\n===================Brightness_message_dealwith=================value=%d\n",value);

                    read_from_register(/*3*/FPGA_STATE_REG_03,FPGA_MASTER_VBYONE1);
                    // BX_printf("\n===================Brightness_message_dealwith=================read03=%d\n",MCU_REG_func[FPGA_MASTER_VBYONE1][3]);


                    MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] = value ;

                    MCU_REG_func[FPGA_MASTER_VBYONE1][6] = MCU_REG_func[FPGA_MASTER_VBYONE1][0x40];
                    write_to_register(FPGA_BRIGHT_REG_06, 0xFF,MCU_REG_func[FPGA_MASTER_VBYONE1][6],FPGA_MASTER_VBYONE1);
                    //使能寄存器调亮
                    write_to_register(/*3*/FPGA_STATE_REG_03, 0x04,0x04,FPGA_MASTER_VBYONE1);

                    //开始结果默认失败
                    g_change.sys_send_cmd_result = 1;
                    //命令执行完毕退出来
                    g_change.sys_hand_Bri_flag = 0;
                }
                break;
            }
            default:{
                //跳转到状态3
                g_change.sys_hand_Bri_flag = 0;
            }
        }
    }

    return com_result;
}


/*!
 *  @brief	Checktime()
 *  @param	none
 *  @return	none
 *  @note	none
 */
void fpga_manage::Checktime()
{
    // //    Ouint8 ret;
    // //    TimeBCDType set_time;
    // QString dateExp, timeExp, tmpExp, cmdExp;
    // int year,month,day,hour,minute,second;

    // //    set_time.year = MCU_RAM_CMD[8];//BCD_to_HEC(MCU_RAM6[9]) * 100 + BCD_to_HEC(MCU_RAM6[8]);
    // //    set_time.month = (MCU_RAM_CMD[10]);
    // //    ret =(((MCU_RAM_CMD[9])>>4)&0x0F)*10+((MCU_RAM_CMD[9])&0x0F);
    // //if(ret==20){
    // //    set_time.month|=0x80;
    // //}
    // //    set_time.date = (MCU_RAM_CMD[11]);
    // //    set_time.hour = (MCU_RAM_CMD[12]);
    // //    set_time.minute = (MCU_RAM_CMD[13]);
    // //    set_time.second = (MCU_RAM_CMD[14]);
    // //    set_time.week = (MCU_RAM_CMD[15]);

    // //ret = PCF8563_Set(&set_time);


    // year = BCD_to_HEC(MCU_RAM_CMD[8]) + BCD_to_HEC(MCU_RAM_CMD[9]) * 100;
    // month = BCD_to_HEC(MCU_RAM_CMD[10]);
    // day = BCD_to_HEC(MCU_RAM_CMD[11]);
    // hour = BCD_to_HEC(MCU_RAM_CMD[12]);
    // minute = BCD_to_HEC(MCU_RAM_CMD[13]);
    // second = BCD_to_HEC(MCU_RAM_CMD[14]);

    // //BX_printf("\n\n(Checktime)  year:%d month:%d day:%d hour:%d minute:%d second:%d\n ",year,month,day,hour,minute,second) ;

    // dateExp = QString("%1-%2-%3").arg(year,0,10).arg(month,0,10).arg(day,0,10);
    // timeExp = QString("%1:%2:%3").arg(hour,0,10).arg(minute,0,10).arg(second,0,10);

    // tmpExp = dateExp + QString(" ") + timeExp; //不能加week date命令标准格式为date “2013-1-1 12:14:32”
    // cmdExp = QString("date \"") + tmpExp + QString("\";hwclock -wu"); //设置系统时间并同步RTC时间

    // Utils::system_mutex(cmdExp,NULL);
    // //    ret = IT8563WE_Set(&set_time);

    // //    if(ret == 0)
    // {
    //     //PCF8563_Set(&set_time);
    //     // IT8563WE_Set(&set_time);
    // }
}

/*!
*  @brief	OnOff_time()
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::OnOff_time()
{
    Ouint8 i;
    //Ouint8  GroupNum;

    GroupNum = MCU_RAM_CMD[8];
    if(GroupNum > 4)
    {
        GroupNum = 4;
    }

    for(i=0;i<4;i++)
    {
        on_flag[i] = 0;
        off_flag[i] = 0;
    }

    for(i=0;i<GroupNum;i++)
    {
        OnHour[i] = BCD_to_HEC(MCU_RAM_CMD[4*i + 9]);
        OnMinute[i] = BCD_to_HEC(MCU_RAM_CMD[4*i + 10]);
        OffHour[i] = BCD_to_HEC(MCU_RAM_CMD[4*i + 11]);
        OffMinute[i] = BCD_to_HEC(MCU_RAM_CMD[4*i + 12]);

        on_flag[i] = 1;
        off_flag[i] = 1;
    }
}


void fpga_manage::Dealwith_mcu_ram(void)
{
    Ouint16 data_len/*,value*/;
    /*Ouint8 buf[4];*/
    //Ouint8 data[10];

    data_len = (MCU_RAM_CMD[7] << 8) | MCU_RAM_CMD[6];
    if(MCU_RAM_CMD[0] == 0xAA)
    {
        switch(MCU_RAM_CMD[1])
        {
        case 1:
            Checktime();
            break;
        case 2:
            OnOff_time();
            if(MCU_RAM_CMD[2] == 0xAA)
            {
                fpga_flash_access();
                //ExFlash_Erase(ONOFF_SEC,ONOFF_SEC);
                p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->ONOFF_SEC,ERASE_4K,1) ;
                //                ExFlash_Erase_Format(FPGA_MASTER_FLASH,ONOFF_SEC,ERASE_4K,1);
                Ouint8 *p_MCU_RAM_CMD = new Ouint8[data_len+8+4] ;
                for(int i=0;i<data_len+8 ;i++){
                    p_MCU_RAM_CMD[4+i] = MCU_RAM_CMD[i];//just for G32 DRV
                }
                p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->ONOFF_ADD,p_MCU_RAM_CMD,data_len+8) ;
                delete p_MCU_RAM_CMD;
                p_MCU_RAM_CMD = NULL;
                //                ExFlash_WR(FPGA_MASTER_FLASH,ONOFF_ADD,&MCU_RAM_CMD[0],data_len+8);
                MCU_REG_func[FPGA_MASTER_VBYONE1][0x42] = 0x01;
            }else if(MCU_RAM_CMD[2] == 0x55)
            {
                fpga_flash_access();
                //ExFlash_Erase(ONOFF_SEC,ONOFF_SEC);
                p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->ONOFF_SEC,ERASE_4K,1) ;
                //                ExFlash_Erase_Format(FPGA_MASTER_FLASH,ONOFF_SEC,ERASE_4K,1);
                MCU_REG_func[FPGA_MASTER_VBYONE1][0x42] = 0x00;
            }
            break;
        case 3:
            //手动调亮不用保存
            if(MCU_RAM_CMD[8] == 0x00 || MCU_RAM_CMD[8] == 0x10){
                ////调用立即调亮状态机
                //获得当前亮度值
                //                MCU_REG[0x40] = MCU_RAM_CMD[9];
                MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] = MCU_RAM_CMD[9];
                //拷贝到当前正在使用的值中
                g_change.sys_Bri_value = MCU_RAM_CMD[9];

                //发送命令值 要求立即响应 则几个网口全部影响
                Brightness_hand_dealwith(0);
                //保存到接收卡上
                //                Brightness_save_rcv();//no care

                ///手动调亮也保存
                if(MCU_RAM_CMD[2] == 0xAA)
                {
                    //手动调亮不用通知变化，只是上电时处理
                    fpga_flash_access();
                    //                    ExFlash_Erase_Format(FPGA_MASTER_FLASH,BRIGHT_SEC,ERASE_4K,1);
                    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_SEC,ERASE_4K,1) ;
                    //                    ExFlash_WR(FPGA_MASTER_FLASH,BRIGHT_ADD,&MCU_RAM_CMD[0],data_len+8);

                    Ouint8 *p_MCU_RAM_CMD = new Ouint8[data_len+8+4] ;
                    for(int i=0;i<data_len+8 ;i++){
                        p_MCU_RAM_CMD[4+i] = MCU_RAM_CMD[i];//just for G32 DRV
                    }

                    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_ADD,p_MCU_RAM_CMD,data_len+8) ;

                    delete p_MCU_RAM_CMD;
                    p_MCU_RAM_CMD = NULL;

                    g_change.sys_Bri_change = 1;
#if 0

                    if(g_RAM_IN_MCU[BOOT_UP_INIT_STATE]& SET_BIT(BOOT_UP_INIT_OVER))
                    {

                        value = (g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]*16)/100;
                        if(value==0){
                            value=0x01;
                        }
                        if(value>=0x10){
                            value=0x10;
                        }
                        if(value!=MCU_REG[0x40]){
                            if((MCU_REG[0x40]*100)/16 >100){
                                g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]=100;
                            }else{
                                if(MCU_REG[0x40]<=1){
                                    MCU_REG[0x40]=1;
                                }
                                if(MCU_RAM_CMD[0x40]<=16){
                                    MCU_RAM_CMD[0x40]=16;
                                }

                                if((MCU_REG[0x40]*100)%16){
                                    g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]=(((MCU_REG[0x40])*100)/16)+1;
                                    if(g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]>100){
                                        g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]=100;
                                    }
                                }else{
                                    g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]=(MCU_REG[0x40]*100)/16;
                                }

                            }

                            data[0]=CMD_DSP_GROUP;
                            data[1]=CMDV_W_SINGLE_PARA;
                            data[2]=0xC0;
                            data[3]=IMAGE_BRIGHTNESS;
                            data[4] = g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]&0xFF;	        //!<数据低字节
                            data[5] = (g_RAM_FROM_DSP_ORIGIN[IMAGE_BRIGHTNESS]>>8)&0xFF;	//!<数据高字节
                            lcd_signal_set_all(&g_run_page,6,data,VALUE_TYPE_DSP);
                        }
                    }

#endif
                }
            }
            else{
                //其他模式调亮或者删除，
                if(MCU_RAM_CMD[2] == 0xAA)
                {
                    fpga_flash_access();
                    //                    ExFlash_Erase_Format(FPGA_MASTER_FLASH,BRIGHT_SEC,ERASE_4K,1);
                    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_SEC,ERASE_4K,1) ;
                    //                    ExFlash_WR(FPGA_MASTER_FLASH,BRIGHT_ADD,&MCU_RAM_CMD[0],data_len+8);
                    Ouint8 *p_MCU_RAM_CMD = new Ouint8[data_len+8+4] ;
                    for(int i=0;i<data_len+8 ;i++){
                        p_MCU_RAM_CMD[4+i] = MCU_RAM_CMD[i];//just for G32 DRV
                    }
                    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_WRITE(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_ADD,p_MCU_RAM_CMD,data_len+8) ;
                    delete p_MCU_RAM_CMD;
                    p_MCU_RAM_CMD = NULL;

                    g_change.sys_Bri_change = 1;
                    //通知主循环存储的亮度表格有变化
                }else if(MCU_RAM_CMD[2] == 0x55)
                {
                    fpga_flash_access();
                    //                    ExFlash_Erase_Format(FPGA_MASTER_FLASH,BRIGHT_SEC,ERASE_4K,1);
                    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_ERASE(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_SEC,ERASE_4K,1) ;
                    g_change.sys_Bri_change = 1;
                }
                g_change.fun_Bri_check_num = 0;
            }

            break;
        default:
            break;
        }
    }
}



void fpga_manage::read_from_register(Ouint8 reg_addr,Ouint8 sel_fpag)
{
    Ouint8 reg_value;


    if(reg_addr > REG_MAX_NUM){
        return;
    }

    if((reg_addr < 0x40)||(reg_addr >= 0x80))
    {
        //读取数据
        read_fpga_register(reg_addr, &reg_value,sel_fpag);
        // printf("reg_addr:0x%02x, reg_value:0x%02x\n", reg_addr, reg_value);
        pthread_mutex_lock(&m_fpga_reg);
        MCU_REG_func[sel_fpag][reg_addr] = reg_value & 0x0FF;
        pthread_mutex_unlock(&m_fpga_reg);
    }
}


void fpga_manage::write_to_register(Ouint8 reg_addr,Ouint8 reg_mask,Ouint8 reg_data,Ouint8 sel_fpag)
{
    Ouint8 reg_value;
    Ouint8 temp;

    //if(MCU_REG[FPGA_INIT_OK] != 0x01){

    //    return;
    //}

    if(reg_addr > REG_MAX_NUM){

        return;
    }

    if((reg_addr < 0x40) ||(reg_addr >= 0x80) )
    {
        read_from_register(reg_addr,sel_fpag);
        pthread_mutex_lock(&m_fpga_reg);
        temp = MCU_REG_func[sel_fpag][reg_addr] & (~reg_mask);
        MCU_REG_func[sel_fpag][reg_addr] = temp | (reg_mask & reg_data);
        pthread_mutex_unlock(&m_fpga_reg);
        reg_value = MCU_REG_func[sel_fpag][reg_addr];
        //

        if(reg_addr == 0x02)
        {
            if((reg_value & 0x04) != 0)
            {
                //Dealwith_mcu_ram();

                reg_value = reg_value & 0xfb;
            }
            if((reg_value & 0x02) != 0)
            {
                //OVP_EDID_Init();
                reg_value = reg_value & 0xfd;
            }

        }

        if(reg_addr == 0x00){
            if((reg_value & 0x04) == 0){
                ScreenState = ScreenOn;
                if(Timeout_flag & 0x02)     //工程时间到，强制黑屏
                {
                    pthread_mutex_lock(&m_fpga_reg);
                    MCU_REG_func[sel_fpag][reg_addr] = MCU_REG_func[sel_fpag][reg_addr] | 0x04;
                    pthread_mutex_unlock(&m_fpga_reg);
                    ScreenState = ScreenOff;
                    reg_value = MCU_REG_func[sel_fpag][reg_addr];
                }
            }else{
                ScreenState = ScreenOff;
            }
            pthread_mutex_lock(&m_fpga_reg);
            MCU_RAM_EXTEND[0x1D] = ScreenState;
            pthread_mutex_unlock(&m_fpga_reg);

            if(reg_value & 0x08){
                search_card_flag = true;
            }else{
                search_card_flag = false;
            }

            if(MCU_REG_func[sel_fpag][0x00] & 0x20){
                wait_new_time = true;
            }else{
                if(wait_new_time == true){
                    new_check_time = true;
                    wait_new_time = false;
                }
            }
        }

        //回写到FPGA中。
        //BX_printf("\n reg_addr : %#x, reg_value : %#x \n",reg_addr,reg_value);
        write_fpga_register(reg_addr, reg_value,sel_fpag , reg_mask);
    }else if(reg_addr < 0x61){

        temp = MCU_REG_func[sel_fpag][reg_addr] & (~reg_mask);
        MCU_REG_func[sel_fpag][reg_addr] = temp | (reg_mask & reg_data);

        if(reg_addr == 0x40){
            //Brightness_hand_dealwith();

        }
    }
}



void fpga_manage::write_fpga_ram(Ouint8* buf,Ouint32 addr,Ouint32 len,Ouint8 ram_num,Ouint8 sel_fpag)
{
#if 1
#ifdef OUTPUT_LEDNET

    Ouint8 cmd_buf[4];
    Ouint8 sel_ram;
    Ouint32 fpga_cmd;
    Ouint32 i;
    int fd ;

    Utils::_spi_mutex.lock();

    //    RAM_addr = (addr >> 24) & 0x0f;
    addr = addr & 0x00ff0fff;
    //使能命名功能
    if(sel_fpag==FPGA_MASTER_VBYONE1){
        p_fpga_manage->setGpioHigLow(2, 30, 1);
        //*(unsigned short *)p_fpga_manage->addr_gpio4 =  GPIO4_CONTENT_L;
        //*(unsigned short *)p_fpga_manage->addr_gpio85 =  GPIO85_CONTENT_H;

        fd = p_fpga_manage->fpga_vbyone1_fd ;
    }

    /*if(addr > 1023){
      ex_addr = 1;
    }else{
      ex_addr = 0;
    }*/


    //CMD_DELAY();

    sel_ram = FPGA_CMD_SEL_RAM;

    //命令值
    fpga_cmd = p_fpga_manage->fpga_cmd_to_spi_data(sel_ram, ram_num , addr ,FPGA_CMD_EN_WR);

    cmd_buf[3] = (fpga_cmd >> 24) & 0x0FF;
    cmd_buf[2] = (fpga_cmd >> 16) & 0x0FF;
    cmd_buf[1] = (fpga_cmd >> 8) & 0x0FF;
    cmd_buf[0] = fpga_cmd & 0x0FF;
    //写命令到FPGA
    //spi_write_nbyte(cmd_buf, 2);
    //spi_write_nbyte_func[sel_fpag](cmd_buf, 2);

    p_fpga_manage->p_fpga_drv->SPI_Transfer_Write(fd ,&cmd_buf[0] , 4) ;

    //CMD_DELAY();

    //写对应数据
    if(sel_fpag==FPGA_MASTER_VBYONE1){
        //EN_SEND_DATA();
        //system("echo 0 >/sys/class/gpio/gpio14/value");
        p_fpga_manage->setGpioHigLow(2, 30, 0);
    }
    //CMD_DELAY();
    //写数据，1个字节一写
    //len = len;
    //spi_write_nbyte(buf, len);
    //spi_write_nbyte_func[sel_fpag](buf, len);
    for(i=0;i<len;i++){
        //p_fpga_manage->p_fpga_drv->SPI_Transfer_Write(fd ,&buf[i] , 1) ;
        //        usleep(10);
    }
    p_fpga_manage->p_fpga_drv->SPI_Transfer_Write(fd ,&buf[0] , len) ;

    if(sel_fpag==FPGA_MASTER_VBYONE1){
        //*(unsigned short *)p_fpga_manage->addr_gpio4 =  GPIO4_CONTENT_H;
        //*(unsigned short *)p_fpga_manage->addr_gpio85 =  GPIO85_CONTENT_H;
    }


    Utils::_spi_mutex.unlock();

#endif
#endif

}


void fpga_manage::read_fpga_ram(Ouint8* buf,Ouint32 addr,Ouint32 len,Ouint8 ram_num,Ouint8 sel_fpag)
{
#if 1
#ifdef OUTPUT_LEDNET

    Ouint8 cmd_buf[4];
    //    Ouint8 RAM_addr ;//,sel_ram=FPGA_CMD_SEL_RAM0;
    Ouint8 sel_ram;
    Ouint32 fpga_cmd;
    Ouint32 i;
    int fd ;

    Utils::_spi_mutex.lock();
    //system("echo 0 >/sys/class/gpio/gpio85/value");
    //    RAM_addr = (addr >> 24) & 0x0f;
    addr = addr & 0x00ff0fff;
    //使能命名功能
    if(sel_fpag==FPGA_MASTER_VBYONE1){
        p_fpga_manage->setGpioHigLow(2, 30, 1);
        //*(unsigned short *)p_fpga_manage->addr_gpio4 =  GPIO4_CONTENT_L;
        //*(unsigned short *)p_fpga_manage->addr_gpio85 =  GPIO85_CONTENT_H;

        fd = p_fpga_manage->fpga_vbyone1_fd ;
    }

    //CMD_DELAY();

    sel_ram = FPGA_CMD_SEL_RAM;

    //命令值
    fpga_cmd = p_fpga_manage->fpga_cmd_to_spi_data(sel_ram, ram_num, addr , FPGA_CMD_EN_RD);

    cmd_buf[3] = (fpga_cmd >> 24) & 0x0FF;
    cmd_buf[2] = (fpga_cmd >> 16) & 0x0FF;
    cmd_buf[1] = (fpga_cmd >> 8) & 0x0FF;
    cmd_buf[0] = fpga_cmd & 0x0FF;
    //写命令到FPGA
    //spi_write_nbyte(cmd_buf, 2);
    //spi_write_nbyte_func[sel_fpag](cmd_buf, 2);

    p_fpga_manage->p_fpga_drv->SPI_Transfer_Write(fd ,&cmd_buf[0] , 4) ;

    //CMD_DELAY();

    //写对应数据
    if(sel_fpag==FPGA_MASTER_VBYONE1){
        p_fpga_manage->setGpioHigLow(2, 30, 0);
    }


    //CMD_DELAY();
    //写数据，2个字节一写
    //len = len;
    //spi_read_nbyte(buf, len);
    //spi_read_nbyte_func[sel_fpag](buf, len);
    unsigned char * txbuff = new unsigned char[len];
    for(i=0;i<len;i++){
        txbuff[i] = 0xff ;
        // p_fpga_manage->p_fpga_drv->SPI_Transfer(fd ,&txbuff[i] , &buf[i] ,1) ;
    }
    p_fpga_manage->p_fpga_drv->SPI_Transfer(fd ,&txbuff[0] , &buf[0] ,len) ;

    delete txbuff ;
    if(sel_fpag==FPGA_MASTER_VBYONE1){
        //*(unsigned short *)p_fpga_manage->addr_gpio4 =  GPIO4_CONTENT_H;
        //*(unsigned short *)p_fpga_manage->addr_gpio85 =  GPIO85_CONTENT_H;
    }


    Utils::_spi_mutex.unlock();

#endif
#endif

}


//fuc
void fpga_manage::FPGA_to_RAM(Ouint8 sel_fpag)
{
    read_from_register(FPGA_BYTE0_REG,sel_fpag);
    read_from_register(FPGA_BYTE1_REG,sel_fpag);
    read_from_register(FPGA_BYTE2_REG,sel_fpag);
    read_from_register(FPGA_BYTE3_REG,sel_fpag);
    MCU_RAM_CMD[0x0C] = MCU_REG_func[sel_fpag][FPGA_BYTE0_REG];
    MCU_RAM_CMD[0x0D] = MCU_REG_func[sel_fpag][FPGA_BYTE1_REG];
    MCU_RAM_CMD[0x0E] = MCU_REG_func[sel_fpag][FPGA_BYTE2_REG];
    MCU_RAM_CMD[0x0F] = MCU_REG_func[sel_fpag][FPGA_BYTE3_REG];
}

//fun
void fpga_manage::update_eth_state(Ouint8 sel_fpag)
{
    Ouint8 state1,state2,state3;
    Ouint8 temp1,temp2,temp3,temp4;

    read_from_register(FPGA_STATE1_REG,sel_fpag);
    read_from_register(FPGA_STATE3_REG,sel_fpag);

    temp1 = MCU_REG_func[sel_fpag][FPGA_STATE1_REG] & 0x03; //!<get status(netport 1,2)
    temp2 = MCU_REG_func[sel_fpag][FPGA_STATE1_REG] & 0x0c; //!<get status(netport 3,4)
    temp3 = MCU_REG_func[sel_fpag][FPGA_STATE1_REG] & 0xf0; //!<get status(netport 5-8)
    temp4 = MCU_REG_func[sel_fpag][FPGA_STATE3_REG]; //!<get status(netport 9-16)

    state1 = MCU_RAM_PARA_func[sel_fpag][eth_state1];
    state2 = MCU_RAM_PARA_func[sel_fpag][eth_state2];
    state3 = MCU_RAM_PARA_func[sel_fpag][eth_state3];

    state1 = state1 & 0xe4;//!<clear net 1-4
    state2 = state2 & 0xf0;//!<clear net 5-8
    state3 = state3 & 0x00;//!<clear net 9-16

    state1 = state1 | (temp1 | (temp2<<1));
    state2 = state2 | (temp3>>4);
    state3 = state3 | temp4;

    if(MCU_RAM_PARA_func[sel_fpag][eth_state1] != state1){
        MCU_RAM_PARA_func[sel_fpag][eth_state1] = state1;
        //同步到FPGA中
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][eth_state1],eth_state1,1,PARA_RAM,sel_fpag);

    }

    if(MCU_RAM_PARA_func[sel_fpag][eth_state2] != state2){
        MCU_RAM_PARA_func[sel_fpag][eth_state2] = state2;
        //同步到FPGA中
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][eth_state2],eth_state2,1,PARA_RAM,sel_fpag);
    }

    if(MCU_RAM_PARA_func[sel_fpag][eth_state3] != state3){
        MCU_RAM_PARA_func[sel_fpag][eth_state3] = state3;
        //同步到FPGA中
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][eth_state3],eth_state3,1,PARA_RAM,sel_fpag);
    }


    //
    if((MCU_RAM_PARA_func[sel_fpag][eth_state1]&0x01) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x64] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x65] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x64],0x64,2,PARA_RAM,sel_fpag);
        //多功能卡
        MCU_RAM_PARA_func[sel_fpag][0x68] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x68],0x68,1,PARA_RAM,sel_fpag);
    }
    if((MCU_RAM_PARA_func[sel_fpag][eth_state1]&0x02) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x66] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x67] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x66],0x66,2,PARA_RAM,sel_fpag);
        //多功能卡
        MCU_RAM_PARA_func[sel_fpag][0x6A] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x6A],0x6A,1,PARA_RAM,sel_fpag);
    }
    if((MCU_RAM_PARA_func[sel_fpag][eth_state1]&0x08) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x6C] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x6D] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x6C],0x6C,2,PARA_RAM,sel_fpag);
        //多功能卡
        MCU_RAM_PARA_func[sel_fpag][0x70] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x70],0x70,1,PARA_RAM,sel_fpag);
    }
    if((MCU_RAM_PARA_func[sel_fpag][eth_state1]&0x10) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x6E] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x6F] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x6E],0x6E,2,PARA_RAM,sel_fpag);
        //多功能卡
        MCU_RAM_PARA_func[sel_fpag][0x72] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x72],0x72,1,PARA_RAM,sel_fpag);
    }
    //网口5
    if((MCU_RAM_PARA_func[sel_fpag][eth_state2]&0x01) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x230] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x231] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x230],0x230,2,PARA_RAM,sel_fpag);
        //多功能卡
        MCU_RAM_PARA_func[sel_fpag][0x232] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x232],0x232,1,PARA_RAM,sel_fpag);
    }
    //网口6
    if((MCU_RAM_PARA_func[sel_fpag][eth_state2]&0x02) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x234] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x235] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x234],0x234,2,PARA_RAM,sel_fpag);
        //多功能卡
        MCU_RAM_PARA_func[sel_fpag][0x236] = 0 ;
        write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x236],0x236,1,PARA_RAM,sel_fpag);
    }

    if (g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM > 6)
    {
    //网口7
        if((MCU_RAM_PARA_func[sel_fpag][eth_state2]&0x04) == 0){
            MCU_RAM_PARA_func[sel_fpag][0x238] = 0 ;
            MCU_RAM_PARA_func[sel_fpag][0x239] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x238],0x238,2,PARA_RAM,sel_fpag);
            //多功能卡
            MCU_RAM_PARA_func[sel_fpag][0x23A] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x23A],0x23A,1,PARA_RAM,sel_fpag);
        }
        //网口8
        if((MCU_RAM_PARA_func[sel_fpag][eth_state2]&0x08) == 0){
            MCU_RAM_PARA_func[sel_fpag][0x23C] = 0 ;
            MCU_RAM_PARA_func[sel_fpag][0x23D] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x23C],0x23C,2,PARA_RAM,sel_fpag);
            //多功能卡
            MCU_RAM_PARA_func[sel_fpag][0x23E] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x23E],0x23E,1,PARA_RAM,sel_fpag);
        }

        //网口9
        if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x01) == 0){
            MCU_RAM_PARA_func[sel_fpag][ETH8_RCVL] = 0 ;
            MCU_RAM_PARA_func[sel_fpag][ETH8_RCVH] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH8_RCVL],ETH8_RCVL,2,PARA_RAM,sel_fpag);
            //多功能卡
            MCU_RAM_PARA_func[sel_fpag][ETH8_VMF] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH8_VMF],ETH8_VMF,1,PARA_RAM,sel_fpag);
        }
        //网口10
        if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x02) == 0){
            MCU_RAM_PARA_func[sel_fpag][ETH9_RCVL] = 0 ;
            MCU_RAM_PARA_func[sel_fpag][ETH9_RCVH] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH9_RCVL],ETH9_RCVL,2,PARA_RAM,sel_fpag);
            //多功能卡
            MCU_RAM_PARA_func[sel_fpag][ETH9_VMF] = 0 ;
            write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH9_VMF],ETH9_VMF,1,PARA_RAM,sel_fpag);
        }

        if (g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM > 10)
        {

            //网口11
            if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x04) == 0){
                MCU_RAM_PARA_func[sel_fpag][ETH10_RCVL] = 0 ;
                MCU_RAM_PARA_func[sel_fpag][ETH10_RCVH] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH10_RCVL],ETH10_RCVL,2,PARA_RAM,sel_fpag);
                //多功能卡
                MCU_RAM_PARA_func[sel_fpag][ETH10_VMF] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH10_VMF],ETH10_VMF,1,PARA_RAM,sel_fpag);
            }
            //网口12
            if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x08) == 0){
                MCU_RAM_PARA_func[sel_fpag][ETH11_RCVL] = 0 ;
                MCU_RAM_PARA_func[sel_fpag][ETH11_RCVH] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH11_RCVL],ETH11_RCVL,2,PARA_RAM,sel_fpag);
                //多功能卡
                MCU_RAM_PARA_func[sel_fpag][ETH11_VMF] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH11_VMF],ETH11_VMF,1,PARA_RAM,sel_fpag);
            }

            //网口13
            if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x10) == 0){
                MCU_RAM_PARA_func[sel_fpag][ETH12_RCVL] = 0 ;
                MCU_RAM_PARA_func[sel_fpag][ETH12_RCVH] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH12_RCVL],ETH12_RCVL,2,PARA_RAM,sel_fpag);
                //多功能卡
                MCU_RAM_PARA_func[sel_fpag][ETH12_VMF] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH12_VMF],ETH12_VMF,1,PARA_RAM,sel_fpag);
            }
            //网口14
            if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x20) == 0){
                MCU_RAM_PARA_func[sel_fpag][ETH13_RCVL] = 0 ;
                MCU_RAM_PARA_func[sel_fpag][ETH13_RCVH] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH13_RCVL],ETH13_RCVL,2,PARA_RAM,sel_fpag);
                //多功能卡
                MCU_RAM_PARA_func[sel_fpag][ETH13_VMF] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH13_VMF],ETH13_VMF,1,PARA_RAM,sel_fpag);
            }
            //网口15
            if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x40) == 0){
                MCU_RAM_PARA_func[sel_fpag][ETH14_RCVL] = 0 ;
                MCU_RAM_PARA_func[sel_fpag][ETH14_RCVH] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH14_RCVL],ETH14_RCVL,2,PARA_RAM,sel_fpag);
                //多功能卡
                MCU_RAM_PARA_func[sel_fpag][ETH14_VMF] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH14_VMF],ETH14_VMF,1,PARA_RAM,sel_fpag);
            }
            //网口16
            if((MCU_RAM_PARA_func[sel_fpag][eth_state3]&0x80) == 0){
                MCU_RAM_PARA_func[sel_fpag][ETH15_RCVL] = 0 ;
                MCU_RAM_PARA_func[sel_fpag][ETH15_RCVH] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH15_RCVL],ETH15_RCVL,2,PARA_RAM,sel_fpag);
                //多功能卡
                MCU_RAM_PARA_func[sel_fpag][ETH15_VMF] = 0 ;
                write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][ETH15_VMF],ETH15_VMF,1,PARA_RAM,sel_fpag);
            }
        }
    }
}




//
Ouint8 fpga_manage::get_eth_param_addr(Ouint8 eth_num,Ouint16* addrx,Ouint16* addry,Ouint16* addrw,Ouint16* addrh)
{
    switch(eth_num){
    case 0:
        *addrx = ETH0_X;
        break;
    case 1:
        *addrx = ETH1_X;
        break;
    case 2:
        *addrx = ETH2_X;
        break;
    case 3:
        *addrx = ETH3_X;
        break;
    case 4:
        *addrx = ETH4_X;
        break;
    case 5:
        *addrx = ETH5_X;
        break;
    case 6:
        *addrx = ETH6_X;
        break;
    case 7:
        *addrx = ETH7_X;
        break;

    case 8:
        *addrx = ETH8_X;
        break;
    case 9:
        *addrx = ETH9_X;
        break;
    case 10:
        *addrx = ETH10_X;
        break;
    case 11:
        *addrx = ETH11_X;
        break;
    case 12:
        *addrx = ETH12_X;
        break;
    case 13:
        *addrx = ETH13_X;
        break;
    case 14:
        *addrx = ETH14_X;
        break;
    case 15:
        *addrx = ETH15_X;
        break;
    default:
        *addrx = ETH0_X;
        //return 1;//出错
        break;
    }

    *addry = *addrx + 2;//!<垂直起始
    *addrw = *addrx + 4;//!<水平宽度
    *addrh = *addrx + 6;//!<垂直高度

    return 0;
}



//cal lcd_x,y
//get min _x _y
Ouint8 fpga_manage::get_eth_min_x_y(Ouint8 sel_fpag,Ouint16* min_x,Ouint16* min_y)
{
    Ouint16 i,addrx,addry,addrw,addrh;
    Ouint16 value_x=0,value_y=0;
    Ouint8 *p_mcu_ram_para_fun = (Ouint8 *)(MCU_RAM_PARA_func[sel_fpag]);

    //port0
    get_eth_param_addr(0,&addrx,&addry,&addrw,&addrh);
    value_x = SPLIT_8_to_16(p_mcu_ram_para_fun,addrx);
    value_y = SPLIT_8_to_16(p_mcu_ram_para_fun,addry);

    //port1
    for(i=1;i<g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;i++){

        get_eth_param_addr(i,&addrx,&addry,&addrw,&addrh);

        if(value_x > SPLIT_8_to_16(p_mcu_ram_para_fun,addrx)){
            value_x = SPLIT_8_to_16(p_mcu_ram_para_fun,addrx);
        }

        if(value_y > SPLIT_8_to_16(p_mcu_ram_para_fun,addry)){
            value_y = SPLIT_8_to_16(p_mcu_ram_para_fun,addry);
        }

    }

    *min_x = value_x;
    *min_y = value_y;

    return 0;
}


//cal lcd_x,y
//get max _w _h
Ouint8 fpga_manage::get_eth_max_border(Ouint8 sel_fpag,Ouint16* max_w,Ouint16* max_h)
{
    Ouint16 i,addrx,addry,addrw,addrh;
    Ouint16 value_w,value_h;
    Ouint8 *p_mcu_ram_para_fun = (Ouint8 *)(MCU_RAM_PARA_func[sel_fpag]);

    //port0
    get_eth_param_addr(0,&addrx,&addry,&addrw,&addrh);
    value_w = SPLIT_8_to_16(p_mcu_ram_para_fun,addrx) + SPLIT_8_to_16(p_mcu_ram_para_fun,addrw);
    value_h = SPLIT_8_to_16(p_mcu_ram_para_fun,addry) + SPLIT_8_to_16(p_mcu_ram_para_fun,addrh);

    //port1
    for(i=1;i<g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;i++){

        get_eth_param_addr(i,&addrx,&addry,&addrw,&addrh);

        if(value_w < SPLIT_8_to_16(p_mcu_ram_para_fun,addrx) + SPLIT_8_to_16(p_mcu_ram_para_fun,addrw) ){
            value_w = SPLIT_8_to_16(p_mcu_ram_para_fun,addrx) + SPLIT_8_to_16(p_mcu_ram_para_fun,addrw);
        }

        if(value_h < SPLIT_8_to_16(p_mcu_ram_para_fun,addry) + SPLIT_8_to_16(p_mcu_ram_para_fun,addrh)){
            value_h = SPLIT_8_to_16(p_mcu_ram_para_fun,addry) + SPLIT_8_to_16(p_mcu_ram_para_fun,addrh);
        }

    }

    *max_w = value_w;
    *max_h = value_h;

    return 0;
}


//cal lcd_x,y
//get max _x _y
Ouint8 fpga_manage::get_eth_lcd_x_y(Ouint8 sel_fpag,Ouint16* lcd_x,Ouint16* lcd_y)
{
    Ouint16 value_x,value_y;
    Ouint8 *p_mcu_ram_para_fun = (Ouint8 *)(MCU_RAM_PARA_func[sel_fpag]);


    value_x = SPLIT_8_to_16(p_mcu_ram_para_fun,ETH_LCD_X);
    value_y = SPLIT_8_to_16(p_mcu_ram_para_fun,ETH_LCD_Y);

    *lcd_x = value_x;
    *lcd_y = value_y;

    return 0;
}


//cal lcd_x,y
//get max _w _h
Ouint8 fpga_manage::get_eth_lcd_w_h(Ouint8 sel_fpag,Ouint16* lcd_w,Ouint16* lcd_h)
{
    Ouint16 value_w,value_h;
    Ouint8 *p_mcu_ram_para_fun = (Ouint8 *)(MCU_RAM_PARA_func[sel_fpag]);

    value_w = SPLIT_8_to_16(p_mcu_ram_para_fun,ETH_LCD_W);
    value_h = SPLIT_8_to_16(p_mcu_ram_para_fun,ETH_LCD_H);

    *lcd_w = value_w;
    *lcd_h = value_h;

    return 0;
}


//fun
bool fpga_manage::check_fpga_ram_param(Ouint8 sel_fpag)
{
    //check net x,y,w,h
    Ouint16 i,addrx,addry,addrw,addrh;
    Ouint16 value;

    for(i=0;i<g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;i++){
        get_eth_param_addr(i,&addrx,&addry,&addrw,&addrh);

        //BX_printf("\n addrx = %#x addry = %#x  addrw = %#x addrh = %#x \n",addrx,addry,addrw,addrh);
        read_fpga_ram((Ouint8*)&value,addrx,2,PARA_RAM,sel_fpag);


        //BX_printf("\n addrx = %#x (%#x)(%#x),---i=%#x\n",addrx,value,SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrx),i);
        if(value !=  SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrx)){

            return false;
        }

        read_fpga_ram((Ouint8*)&value,addry,2,PARA_RAM,sel_fpag);
        //BX_printf("\n addry = %#x (%#x)(%#x),---i=%#x\n",addry,value,SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addry),i);
        if(value != SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addry)){

            return false;
        }

        read_fpga_ram((Ouint8*)&value,addrw,2,PARA_RAM,sel_fpag);
        //BX_printf("\n addrw = %#x (%#x)(%#x),---i=%#x\n",addrw,value,SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrw),i);
        if(value != SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrw)){

            return false;
        }

        read_fpga_ram((Ouint8*)&value,addrh,2,PARA_RAM,sel_fpag);
        //BX_printf("\n addrh = %#x (%#x)(%#x),---i=%#x\n",addrh,value,SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrh),i);
        if(value != SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrh)){

            return false;
        }

    }


    //check fram_size


    for(i=0;i<g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;i++){


        read_fpga_ram((Ouint8*)&value,ETH0_FRAME_SIZE+i*4,2,PARA_RAM,sel_fpag);
        //BX_printf("\n fram size  (%#x)(%#x)---%#x\n",value,SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],(ETH0_FRAME_SIZE+i*4)),i);
        if(value != SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],(ETH0_FRAME_SIZE+i*4))){

            return false;
        }

        read_fpga_ram((Ouint8*)&value,ETH0_FRAME_SIZE+2+i*4,2,PARA_RAM,sel_fpag);
        //BX_printf("\n fram size  (%#x)(%#x)---%#x\n",value,SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],(ETH0_FRAME_SIZE+2+i*4)),i);
        if(value != SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],(ETH0_FRAME_SIZE+2+i*4))){

            return false;
        }
    }

    //    Ouint8 phy_rx[RAM_MAX_LEN];
    //    for(i=0;i<RAM_MAX_LEN;i++){

    //        phy_rx[i] = 0;
    //    }
    //    read_fpga_ram(phy_rx,ETH0_FRAME_SIZE,g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM*4,0,sel_fpag);

    //    for(i=0;i<RAM_MAX_LEN;i++){
    //        if( (i%16) == 0){
    //            BX_printf("\n");

    //        }

    //        BX_printf(" %#x ", phy_rx[i]);

    //    }

    return true;
}



//fun
void fpga_manage::eth_param_init(Ouint8 flag,Ouint8 sel_fpag)
{
    Ouint16 i,addrx,addry,addrw,addrh;

    for(i=0;i<g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;i++){
        get_eth_param_addr(i,&addrx,&addry,&addrw,&addrh);//get netport_addr

        if(flag == 1){
            MCU_RAM_PARA_func[sel_fpag][addrx] = 0;
            MCU_RAM_PARA_func[sel_fpag][addrx+1] = 0;
            MCU_RAM_PARA_func[sel_fpag][addry] = 0;
            MCU_RAM_PARA_func[sel_fpag][addry+1] = 0;
            MCU_RAM_PARA_func[sel_fpag][addrw] = 0;
            MCU_RAM_PARA_func[sel_fpag][addrw+1] = 0x05;
            MCU_RAM_PARA_func[sel_fpag][addrh] = 0;
            MCU_RAM_PARA_func[sel_fpag][addrh+1] = 0x02;
        }else{
            //JUST GOR G32
            /* MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][LCD_VBY_X] = SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_X)&0xFF;
          MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][LCD_VBY_X+1] = (SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_X)>>8)&0xFF;
          MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][LCD_VBY_Y] = SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_Y)&0xFF;
          MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][LCD_VBY_Y+1] = (SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_Y)>>8)&0xFF;

          BX_printf("\n eth_param_init (%d) \n",SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_X)) ;

          value = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addrx) ;
          value +=SPLIT_8_to_16(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],LCD_VBY_X);

          MCU_RAM_PARA_func[sel_fpag][addrx] = (value&0xFF) ;
          MCU_RAM_PARA_func[sel_fpag][addrx+1] = (value>>8)&0xFF ;

          value = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpag],addry) ;
          value +=SPLIT_8_to_16(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],LCD_VBY_Y);

          MCU_RAM_PARA_func[sel_fpag][addry] = (value&0xFF) ;
          MCU_RAM_PARA_func[sel_fpag][addry+1] = (value>>8)&0xFF ;*/
        }

        //ram_p_mcu[ETH0_H_X + i*6] = MCU_RAM_PARA[addrx] | ((uint16)MCU_RAM_PARA[addrx+1]) <<8;
        //ram_p_mcu[ETH0_V_Y + i*6] = MCU_RAM_PARA[addry] | ((uint16)MCU_RAM_PARA[addry+1]) <<8;
        //ram_p_mcu[ETH0_H_WIDTH + i*6] = MCU_RAM_PARA[addrw] | ((uint16)MCU_RAM_PARA[addrw+1]) <<8;
        //ram_p_mcu[ETH0_V_HEIGHT + i*6] = MCU_RAM_PARA[addrh] | ((uint16)MCU_RAM_PARA[addrh+1]) <<8;
    }


}



//fun
void fpga_manage::fpga_flash_access()
{


}


//fun
void fpga_manage::record_onoff_time(Ouint8 sel_fpag)
{
    Ouint8 equ_type;

    if((MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] != 0x03)&&(sel_fpag!=FPGA_FLASH_VBYONE1)){
        return ;
    }

    fpga_flash_access();
    //ExFlash_RD(FPGA_MASTER_FLASH,ONOFF_ADD,1,&equ_type);
    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->ONOFF_ADD,1,&equ_type) ;
    if(equ_type == 0xAA)
    {
        //ExFlash_RD(FPGA_MASTER_FLASH,ONOFF_ADD,50,MCU_RAM_CMD);
        p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->ONOFF_ADD,50,MCU_RAM_CMD) ;
        OnOff_time();
        MCU_REG_func[FPGA_MASTER_VBYONE1][0x42] = 0x01;//g_fpga_change.fun_onoff_enable;
    }

}

/*!
*  @brief	Brightness_init()
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_init(Ouint8 *data)
{
    Ouint32 i;

    g_BrightnessMode = data[8];

    //默认调亮任务不启动
    g_change.sys_Bri_task = 0;

    g_change.sys_Bri_rcv_num = 0xFFFFFFFF;
    g_change.sys_Bri_rcv_change = 0;

    g_Bri_table_change = 0xFF;

    switch(g_BrightnessMode){
    case 0x10:
    case 0x00:{  ///手动调亮
        ////周期性处理，10s周期
        //获得当前亮度值
        MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] = data[9];
        //拷贝到当前正在使用的值中
        g_change.sys_Bri_value = data[9];

        //g_change.sys_Bri_task_time = G_timeTicks;
        g_change.sys_Bri_task = 1;
        //上电默认0次
        g_change.sys_Bri_times = 0;
        break;
    }
    case 0x11:
    case 0x01:{  ///定时调亮

        for(i = 0; i < 48 ; i++)
        {
            HalfHourValue[i] = data[i+9];
        }

        //g_change.sys_Bri_task_time = G_timeTicks;
        g_change.sys_Bri_task = 1;
        break;
    }
    case 0x02:{  ///自动调亮
        //g_change.sys_Bri_task_time = G_timeTicks;
        g_change.sys_Bri_task = 1;
        break;
    }
    default:{
        g_change.sys_Bri_task = 0;
    }

    }

}




//fun
void fpga_manage::record_bright_change(void)
{
#if 1
    Ouint8 equ_type;

    if((MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] != 0x03)
        #if (defined OUTPUT_BOARD_2)
            &&
            (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] != 0x03)
        #endif
            ){
        return ;
    }



    fpga_flash_access();
    //查看存储标记字节是否有效
    // ExFlash_RD(BRIGHT_ADD,1,&equ_type);
    //    ExFlash_RD(FPGA_MASTER_FLASH,BRIGHT_ADD,1,&equ_type);
    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_ADD,1,&equ_type) ;
    if(equ_type == 0xAA)
    {
        //读取存储的数据
        //ExFlash_RD(BRIGHT_ADD,57,MCU_RAM6);
        //        ExFlash_RD(FPGA_MASTER_FLASH,BRIGHT_ADD,57,MCU_RAM_CMD);
        p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->BRIGHT_ADD,57,MCU_RAM_CMD) ;
        //无此函数 暂放
        Brightness_init(MCU_RAM_CMD);
    }
    else{

        //默认调亮任务不启动
        g_change.sys_Bri_task = 0;
        //默认最高亮度
        g_change.sys_Bri_value = 16;
    }
#endif

}


//fun
void fpga_manage::record_check_time(void)
{

    Ouint8 equ_type,crc_xor;
    //    Ouint8  timeout_buf[75];

    if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] != 0x03){
        return ;
    }
    Timeout_flag = 0;

    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,1,&equ_type);
    if(equ_type == 0xAA){
        p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(FPGA_FLASH_VBYONE1,g_Global->TIME_FLAG_ADD,102,timeout_buf);
        crc_xor = Utils::BCC(timeout_buf, 74);
        if(timeout_buf[74] == crc_xor){
            start_time.year = BCD_to_HEC(timeout_buf[43])*100 + BCD_to_HEC(timeout_buf[42]);
            start_time.month = BCD_to_HEC(timeout_buf[44]);
            start_time.date = BCD_to_HEC(timeout_buf[45]);
            start_time.hour = BCD_to_HEC(timeout_buf[46]);
            start_time.minute = BCD_to_HEC(timeout_buf[47]);
            start_time.second = BCD_to_HEC(timeout_buf[48]);
            start_time.week = BCD_to_HEC(timeout_buf[49]);


            check_time.year = BCD_to_HEC(timeout_buf[51])*100 + BCD_to_HEC(timeout_buf[50]);
            check_time.month = BCD_to_HEC(timeout_buf[52]);
            check_time.date = BCD_to_HEC(timeout_buf[53]);
            check_time.hour = BCD_to_HEC(timeout_buf[54]);
            check_time.minute = BCD_to_HEC(timeout_buf[55]);
            check_time.second = BCD_to_HEC(timeout_buf[56]);
            check_time.week = BCD_to_HEC(timeout_buf[57]);

            Timeout_flag = 0x01;
        }
    }
    BX_printf("\n Timeout_flag = %#x ,equ_type = %#x , timeout[84]=%#x\n",Timeout_flag , equ_type,timeout_buf[84]);

}



//fun
void fpga_manage::get_control_uid(/*int fd ,*/Ouint8 sel_fpag)
{
    Ouint32 n;
    //Ouint8  flash_uid[8] ;

    for(n = 0; n < sizeof(flash_uid);n++){
        flash_uid[n] = 0x11;
    }
    //SSTF016B_RD_UID(g_UID);
    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);

    for(n = 0; n < 8; n++)
    {
        write_to_register((0x20+n), 0xff,flash_uid[n],sel_fpag);
    }

    //
    BX_printf("\n\n flash_uid = %#x,%#x,%#x,%#x,%#x,%#x,%#x,%#x\n\n",flash_uid[0],flash_uid[1],flash_uid[2],flash_uid[3],
          flash_uid[4],flash_uid[5],flash_uid[6],flash_uid[7]) ;


    device_id = Utils::calcCRC32(flash_uid,sizeof(flash_uid));
    BX_printf("\n device_id = %#x \n",device_id);

}

//for OUT2 LCD_X
void  fpga_manage::G32_mcu_set_lcd_x_y_para(Ouint8 sel_fpag)
{
    Ouint8 *p_mcu_ram_back_eth_para = MCU_RAM_ETH_BACK_PARA_func[FPGA_MASTER_VBYONE2];

#if (defined OUTPUT_BOARD_2)

    if(sel_fpag == FPGA_MASTER_VBYONE1){
        return ;
    }

    if( SPLIT_8_to_16(p_mcu_ram_back_eth_para,ETH_LCD_X) ==
            SPLIT_8_to_16(fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],ETH_LCD_X) +
            SPLIT_8_to_16(fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],ETH_LCD_W))
    {
        //set OUT2 LCD_X _Y zero
        INIT_16_to8(0,fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2],ETH_LCD_X) ;
        INIT_16_to8(0,fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2],ETH_LCD_Y) ;
    }


    if( SPLIT_8_to_16(p_mcu_ram_back_eth_para,ETH_LCD_Y) ==
            SPLIT_8_to_16(fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],ETH_LCD_Y) +
            SPLIT_8_to_16(fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],ETH_LCD_H))
    {
        //set OUT2 LCD_X _Y zero
        INIT_16_to8(0,fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2],ETH_LCD_X) ;
        INIT_16_to8(0,fpga_manage::MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2],ETH_LCD_Y) ;
    }

#endif

}

void  fpga_manage::G32_mcu_set_net_para(Ouint8 sel_fpag){


}


//just for power on for G32
void  fpga_manage::G32_back_mcu_set_net_para(Ouint8 sel_fpag){

}




//fun
/*!
* @brief   FPGA init
* @param
* @return	NONE
* @note
*/
void  fpga_manage::fpgainit(Ouint8 sel_fpag)
{
    Ouint32 i;
    //    int fd = 0;
    //Ouint8 value;
    Ouint8 buf[2] ;
    Ouint8 crc_buf[256];

    //M4X_H4X 需要将较验发送给FPGA
    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(sel_fpag+FPGA_FLASH_VBYONE1,g_Global->PARAM1_SEC_ADDR+1,256,crc_buf) ;
    write_fpga_ram(crc_buf,0,256,CRC_RAM,sel_fpag); //donot move

    ///获取UID
    get_control_uid(/*fd,*/sel_fpag);//no care fd
    write_to_register(FPGA_CLEAR_REG,0x40,0x40,sel_fpag);
    write_to_register(FPGA_CLEAR_REG,0x40,0x00,sel_fpag);

    //write_to_register(0x03,0x20,0x20,sel_fpag);

    //add by chenyd
    //write_to_register(0x03,0x20,0x20,sel_fpag);

    //FPGA_INT_GPIO();   暂放
    read_from_register(FPGA_STATE0_REG,sel_fpag);//读取FPGA状态寄存器
    write_to_register(FPGA_STATE0_REG,0x20,0x00,sel_fpag);//清除中断标志

    //fpga_flash_access();

    //读取FLASH型号进行驱动加载
    //SSTF016B_RdID(Manu_ID, &temp);

#if 0
    //读取FPGA UID为激活做准备
    read_from_register(FPGA_UID0_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID1_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID2_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID3_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID4_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID5_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID6_REG);//FPGA UID M2X 要求读取FPGA UID
    read_from_register(FPGA_UID7_REG);//FPGA UID M2X 要求读取FPGA UID
#endif

    //fpga_flash_access();
    //获取正确的加密值
    //g_change.sys_secret_flag = set_Secret_Exflash_AMU();

    //读取对应的EDID数据
    //OVP_EDID_Init();
    //使能I2C1
    //I2C_Configuration();
    //记录工程运行时间
    //record_check_time();

    //record_bright_change();
    //    record_onoff_time(fd,sel_fpag);//no care fd
    //record_onoff_time(sel_fpag+FPGA_FLASH_VBYONE1);//no care fd

    read_from_register(FPGA_JUMP_REG,sel_fpag);
    read_from_register(FPGA_JUMP_REG,sel_fpag);
    read_from_register(FPGA_JUMP_REG,sel_fpag);

    //    fpga_flash_access();
    //ExFlash_RD(FPGA_BASE_FLASH+sel_fpag,RAM1_ADD,1,buf);
    buf[0] = 0xff;
       // if(sel_fpag == FPGA_MASTER_VBYONE1){
    p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(sel_fpag+FPGA_FLASH_VBYONE1,g_Global->RAM1_ADD,1,buf) ;
     //   }
    //    buf[0]=0xFF;
    if(buf[0] == 0xAA){
        //ExFlash_RD(FPGA_BASE_FLASH+sel_fpag,RAM1_ADD+1,1024,MCU_RAM_PARA_func[sel_fpag]);
        p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_VBYONE_READ(sel_fpag+FPGA_FLASH_VBYONE1,g_Global->RAM1_ADD+1,1024,MCU_RAM_PARA_func[sel_fpag]) ;

        //中间只读域清零,32字节
        for(i = 0; i < 32; i++){
            MCU_RAM_PARA_func[sel_fpag][0x60+i] = 0x00;
        }
        //MCU_RAM_PARA[123]=0;
        //回写实际状态值
        eth_param_init(0,sel_fpag);

        G32_back_mcu_set_net_para(sel_fpag);
        G32_mcu_set_lcd_x_y_para(sel_fpag);

        //针对 左右两边大小不对称，也就是左边小右边大，需要有LCD_X或者LCD_Y进行偏移只需要调整OUT1就可以了
        if(sel_fpag == FPGA_MASTER_VBYONE1){
            G32_mcu_set_net_para(sel_fpag);
        }


    }else{
        for(i = 0; i < 256; i++){
            MCU_RAM_PARA_func[sel_fpag][i] = RAM1[i];
        }
        //一般拿到卡之后 会进行接收卡设备 此时不再进行PC备份扇区参数更新
        //#if 0
        //暂时默认网口帧大小[0x128--0x146]
        MCU_RAM_PARA_func[sel_fpag][0x128]=0x76;MCU_RAM_PARA_func[sel_fpag][0x129]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x12A]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x12B]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x12C]=0x76;MCU_RAM_PARA_func[sel_fpag][0x12D]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x12E]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x12F]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x130]=0x76;MCU_RAM_PARA_func[sel_fpag][0x131]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x132]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x133]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x134]=0x76;MCU_RAM_PARA_func[sel_fpag][0x135]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x136]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x137]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x138]=0x76;MCU_RAM_PARA_func[sel_fpag][0x139]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x13A]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x13B]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x13C]=0x76;MCU_RAM_PARA_func[sel_fpag][0x13D]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x13E]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x13F]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x140]=0x76;MCU_RAM_PARA_func[sel_fpag][0x141]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x142]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x143]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x144]=0x76;MCU_RAM_PARA_func[sel_fpag][0x145]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x146]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x147]=0x01;

        MCU_RAM_PARA_func[sel_fpag][0x148]=0x76;MCU_RAM_PARA_func[sel_fpag][0x149]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x14A]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x14B]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x14C]=0x76;MCU_RAM_PARA_func[sel_fpag][0x14D]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x14E]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x14F]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x150]=0x76;MCU_RAM_PARA_func[sel_fpag][0x151]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x152]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x153]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x154]=0x76;MCU_RAM_PARA_func[sel_fpag][0x155]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x156]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x157]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x158]=0x76;MCU_RAM_PARA_func[sel_fpag][0x159]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x15A]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x15B]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x15C]=0x76;MCU_RAM_PARA_func[sel_fpag][0x15D]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x15E]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x15F]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x160]=0x76;MCU_RAM_PARA_func[sel_fpag][0x161]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x162]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x163]=0x01;
        MCU_RAM_PARA_func[sel_fpag][0x164]=0x76;MCU_RAM_PARA_func[sel_fpag][0x165]=0x05;
        MCU_RAM_PARA_func[sel_fpag][0x166]=0xD2;MCU_RAM_PARA_func[sel_fpag][0x167]=0x01;

        MCU_RAM_PARA_func[sel_fpag][LCD_VBY_X] = 0x0000;
        MCU_RAM_PARA_func[sel_fpag][LCD_VBY_Y] = 0x0000;
        //#endif
        eth_param_init(1,sel_fpag);

        G32_back_mcu_set_net_para(sel_fpag);
        //init net port
        /*for(i = 0 ; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM ;i++){
             MCU_RAM_PARA_func[sel_fpag][ETH_PORT1_ID + i] = i + 1 + sel_fpag*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;
         }*/

                 BX_printf("\n default para ----------------- \n");
    }

    //init net port
    for(i = 0 ; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM ;i++){
        MCU_RAM_PARA_func[sel_fpag][ETH_PORT1_ID + i] = i + 1 + sel_fpag*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;

    }


    write_fpga_ram(MCU_RAM_PARA_func[sel_fpag],0,1024,PARA_RAM,sel_fpag);

    update_eth_state(sel_fpag);

    // write_to_register(0x02,0x01,0x01,sel_fpag);//update reg
    // write_to_register(0x02,0x01,0x01,sel_fpag);//update reg
    //write_to_register(0x02,0x01,0x01,sel_fpag);//update reg
    //write_to_register(0x02,0x01,0x01,sel_fpag);//update reg

    //write_to_register(0x02,0x01,0x01,sel_fpag);//update reg
    //write_to_register(0x02,0x01,0x01,sel_fpag);//update reg


    //    signal_stable_flag = 1;
    FPGA_to_RAM(sel_fpag);

    write_to_register(FPGA_RAM_REG_02,0x08,0x08,sel_fpag);//!< BIT force to 1
    //read_fpga_ram(MCU_RAM_PARA_func[sel_fpag],0,1024,0,sel_fpag);
    //
    check_fpga_ram_status[sel_fpag] = check_fpga_ram_param(sel_fpag);
    if(check_fpga_ram_status[sel_fpag] == false){
        //reset_fpga_rst(sel_fpag);
        BX_printf("\n check fpga%d ram error ,start to reset .... \n",sel_fpag+1);
    }

}


/*!
*  @brief	Check_TimeOut()
*  @param	none
*  @return	none
*  @note	none
*/
Ouint8 fpga_manage::check_TimeOut_cmp(TimeRealType *ps_time,TimeRealType *rtc_time)
{

    if(ps_time->year < rtc_time->year){
        return 1;
    }else if(ps_time->year > rtc_time->year){
        return 0;
    }

    if(ps_time->month < rtc_time->month){
        return 1;
    }else if(ps_time->month > rtc_time->month){
        return 0;
    }

    if(ps_time->date < rtc_time->date){
        return 1;
    }else if(ps_time->date > rtc_time->date){
        return 0;
    }

    if(ps_time->hour < rtc_time->hour){
        return 1;
    }else if(ps_time->hour > rtc_time->hour){
        return 0;
    }

    if(ps_time->minute < rtc_time->minute){
        return 1;
    }else if(ps_time->minute > rtc_time->minute){
        return 0;
    }

    if(ps_time->second < rtc_time->second){
        return 1;
    }else{
        return 0;
    }
}




//fuc
/*!
*  @brief	Check_TimeOut()
*  @param	none
*  @return	none
*  @note	none
*/
Ouint8 fpga_manage::Check_TimeOut(void)
{
    Ouint8 ret0;
    Ouint8 ret1;

    if(timeout_buf[84] == 0x01){//已经转正
        //g_fpga_change.fun_timeout_enable = FUNCTION_DISABLE;
        Timeout_flag = 0;
        return 0;
    }else if(timeout_buf[101] == 1 || timeout_buf[101] == 0){ //云屏强制加解锁屏指令
        //1 -- 锁屏
        //0 -- 解锁
        return timeout_buf[101];
    }
    else{
        ///比较结束时间是否小于当前时间
        ret0 = check_TimeOut_cmp(&check_time,&read_time);
        ///比较当前时间是否小于开始时间
        ret1 = check_TimeOut_cmp(&read_time,&start_time);

        //只要有一个不满足则有问题。
        return ret0 | ret1;
    }





    //  if(check_time.year < read_time.year){
    //    return 1;
    //  }else if(check_time.year > read_time.year){
    //    return 0;
    //  }
    //
    //  if(check_time.month < read_time.month){
    //    return 1;
    //  }else if(check_time.month > read_time.month){
    //    return 0;
    //  }
    //
    //  if(check_time.date < read_time.date){
    //    return 1;
    //  }else if(check_time.date > read_time.date){
    //    return 0;
    //  }
    //
    //  if(check_time.hour < read_time.hour){
    //    return 1;
    //  }else if(check_time.hour > read_time.hour){
    //    return 0;
    //  }
    //
    //  if(check_time.minute < read_time.minute){
    //    return 1;
    //  }else if(check_time.minute > read_time.minute){
    //    return 0;
    //  }
    //
    //  if(check_time.second < read_time.second){
    //    return 1;
    //  }else{
    //    return 0;
    //  }




}



Ouint8 fpga_manage::IT8563WE_Get(TimeRealType* now)
{
    // QStringList time_list;
    // //    uint16 year_h,year_l;

    // Utils::_system_mutex.lock();
    // QDateTime currentDateTime = QDateTime::currentDateTime();
    // Utils::_system_mutex.unlock();


    // QString time = currentDateTime.toString("yyyy/MM/dd/hh/mm/ss/ddd");

    // //    BX_printf("\n\n in IT8563WE_Get %s\n\n",time.toStdString().data());

    // time_list = time.split('/');

    // //    year_h = (time_list.at(0).toUInt())/100;
    // //    year_l = (time_list.at(0).toUInt())%100;
    // now->year = time_list.at(0).toUInt();//(HEC_to_BCD(year_l) | (HEC_to_BCD(year_h) << 8));

    // now->month = (time_list.at(1).toUInt());//month
    // now->date = (time_list.at(2).toUInt());//date
    // now->hour = (time_list.at(3).toUInt());//hour
    // now->minute = (time_list.at(4).toUInt());//minute
    // now->second = (time_list.at(5).toUInt());//second

    return 0;
}



//fun(deal about time)(engineering funds)
void fpga_manage::Record_Time_Deal(void)
{
    Ouint8 ret;
    Ouint8 overtime = 0;

    if(get_fpga_status() == 0){

        return ;
    }


    ////是否新的工程运行标记
    if(new_check_time == true)
    {
        record_check_time();

        if(Timeout_flag & 0x01)
        {
            overtime = Check_TimeOut();
            Timeout_flag = Timeout_flag | (overtime<<1);
            BX_printf("\n 999999999999=%#x \n",Timeout_flag);
        }

        if(((Timeout_flag & 0x02) == 0) && (ScreenState == ScreenOff))
        {
            write_to_register(0x00,0x04,0x00,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
            write_to_register(0x00,0x04,0x00,FPGA_MASTER_VBYONE2);
#endif
        }else if((Timeout_flag & 0x02) && (ScreenState == ScreenOn)){
            write_to_register(0x00,0x04,0x04,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
            write_to_register(0x00,0x04,0x04,FPGA_MASTER_VBYONE2);
#endif
        }

        new_check_time = false;
    }

    //每秒更新4次RTC时间
    if(G_timeTicks - readtime_ticks > 25)
    {
        ret = IT8563WE_Get(&read_time);
        if(ret != 0)
        {
            //             IT8563WE_Get(&read_time);
        }

        if(Timeout_flag & 0x01)
        {
            overtime = Check_TimeOut();
            Timeout_flag = Timeout_flag | (overtime<<1);
            if((Timeout_flag & 0x02) && (ScreenState == ScreenOn))
            {
                write_to_register(0x00,0x04,0x04,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
                write_to_register(0x00,0x04,0x04,FPGA_MASTER_VBYONE2);
#endif
            }
        }
        //表示工程计时标记 1表示工程计时时间已到  0表示工程时间未到
        MCU_RAM_EXTEND[0x30] = overtime;


        readtime_ticks = G_timeTicks;
    }


}

void fpga_manage::reset_fpga_rst(Ouint8 sel_fpga)
{
    if(sel_fpga == FPGA_MASTER_VBYONE1){

        setGpioHigLow(3, 10, 0) ;
        fpga1_rst_flag = true;
        fpga1_rst_ticks = G_timeTicks;
        fpga_init_rst_times[FPGA_MASTER_VBYONE1]=0x00;
    }


}


void fpga_manage::check_fpga_rst()
{
    if(fpga1_rst_flag == true){
        if(Utils::getTimeSpace(fpga1_rst_ticks) > 200){
            setGpioHigLow(3, 10, 1) ;

            MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] = 0;
            MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE3_REG] = 0;
            check_fpga_phy_status[FPGA_MASTER_VBYONE1] = FPGA_PHY_INIT_START;

            g_change.sys_fpga_delay_time[FPGA_MASTER_VBYONE1] = G_timeTicks;
            fpga1_rst_flag = false;
            fpga_init_step[FPGA_MASTER_VBYONE1] = FPGA_VBO_INIT_START;
            fpga_init_error[FPGA_MASTER_VBYONE1] = 0x00;
                        BX_printf("\n gpio17 set 1! \n") ;
        }
    }

}

Ouint16 fpga_manage::get_port_card_num(Ouint8 port_num)
{
    Ouint8 sel_fpga;
    Ouint16 card_num;


    if(port_num < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
        sel_fpga = FPGA_MASTER_VBYONE1;
    }else if(port_num < g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
        sel_fpga = FPGA_MASTER_VBYONE2;
        port_num = port_num - g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;
    }else{
        return 0;
    }

    switch(port_num){
    case 0:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH0_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH0_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH0_RCVL) ;
        break;
    case 1:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH1_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH1_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH1_RCVL) ;
        break;
    case 2:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH2_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH2_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH2_RCVL) ;
        break;
    case 3:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH3_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH3_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH3_RCVL) ;
        break;
    case 4:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH4_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH4_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH4_RCVL) ;
        break;
    case 5:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH5_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH5_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH5_RCVL);
        break;
    case 6:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH6_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH6_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH6_RCVL);
        break;
    case 7:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH7_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH7_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH7_RCVL);
        break;
    case 8:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH8_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH8_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH8_RCVL);
        break;
    case 9:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH9_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH9_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH9_RCVL);
        break;
    case 10:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH10_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH10_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH10_RCVL);
        break;
    case 11:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH11_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH11_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH11_RCVL);
        break;
    case 12:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH12_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH12_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH12_RCVL);
        break;
    case 13:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH13_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH13_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH13_RCVL);
        break;
    case 14:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH14_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH14_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH14_RCVL);
        break;
    case 15:
        //        card_num = MCU_RAM_PARA_func[sel_fpga][ETH15_RCVL] | (MCU_RAM_PARA_func[sel_fpga][ETH15_RCVH]<<8);
        card_num = SPLIT_8_to_16(MCU_RAM_PARA_func[sel_fpga],ETH15_RCVL);
        break;
    default:
        return 0;
    }


    return card_num;
}


void fpga_manage::get_rcvcard_x_y(int index ,Ouint16 *card_x, Ouint16 *card_y)
{

    return;
}



void fpga_manage::rcv_card_cmd_create(Ouint8 *send_buf, Ouint8 port_num)
{


    return ;
}




void fpga_manage::SmartMapping_deal(void)
{

    return ;
}




void fpga_manage::load_write_ram_cmd_create(Ouint8 port,Ouint8 card_index,Ouint32 ram_addr, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf, bool smart_net)
{
    Ouint8 xor_c;
    Ouint16 length;
    Ouint32 i;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    if(smart_net){
        //msg->dstAddr = 0x0ffe | ((port % 4) << 12);
        msg->dstAddr = 0x0fff; //广播
    }else{
        msg->dstAddr = 0x0000 | ((port % 4) << 12) | card_index;
    }

    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = (port + 1);
    msg->reserved1 = 0;
    msg->cmd = 0x60;

    msg->data[0] = ram_addr & 0xff;
    msg->data[1] = (ram_addr >> 8) & 0x0ff;
    msg->data[2] = (ram_addr >> 16)& 0x0ff;
    msg->data[3] = (ram_addr >> 24) & 0x0ff;

    msg->data[4] = data_len & 0x0ff;
    msg->data[5] = (data_len >> 8) & 0x0ff;

    msg->data[6] = 0x00;
    msg->data[7] = 0x00;

    for(i= 0; i< data_len ;i++) {
        msg->data[8+i] = buf[i];
    }

    length = 18 + data_len;

    xor_c = Utils::BCC((Ouint8 *)send_buf,length);
    msg->data[length - 10] = xor_c;

    g_send_para.send_len = length + 1;

}


Ouint16 fpga_manage::rcv_active_firmware_cmd_create(Ouint8 port, Ouint8 card_index, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf)
{
    Ouint8 xor_c;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;
    msg->dstAddr = 0x0000 | ((port % 4) << 12) | card_index;
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = (port + 1);
    msg->reserved1 = 0;
    msg->cmd = 0xb4;

    for(int i = 0 ; i < data_len ; i++){
        msg->data[i] = buf[i];
    }

    xor_c = Utils::BCC((Ouint8 *)send_buf,data_len + 10);
    msg->data[data_len] = xor_c;

    g_send_para.send_len = data_len + 1 + 10;


    return (data_len + 1 + 10);
}

void fpga_manage::ram_reset_cmd_create(Ouint8 *send_buf,SCAN_PARA *scan_para, Ouint8 port_num)
{
    Ouint8 xor_c;
    Ouint16 data_len;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    msg->dstAddr = 0x0ffe | ((port_num % 4) << 12);
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = port_num + 1;
    msg->reserved1 = 0;
    msg->cmd = 0xA0;


    msg->data[0] = scan_para->targetAddr;//0x01;
    msg->data[1] = scan_para->mask;//0xff;
    msg->data[2] = 0x01;
    msg->data[3] = scan_para->value;//0xff;

    data_len = 14;//!<10+4

    xor_c = Utils::BCC((Ouint8 *)send_buf,data_len);
    msg->data[4] = xor_c;

    g_send_para.send_len = data_len + 1;
}

void fpga_manage::save_para_cmd_create(Ouint8 *send_buf, Ouint8 port_num)
{
    Ouint8 xor_c;
    Ouint16 data_len;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;



    msg->dstAddr = 0x0fff;//广播
    //msg->dstAddr = 0x0ffe | ((port_num % 4) << 12);
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = port_num + 1;//0;
    msg->reserved1 = 0;
    msg->cmd = 0x81;


    msg->data[0] = 0xff;
    msg->data[1] = 0;


    data_len = 12;//!<10+2

    xor_c = Utils::BCC((Ouint8 *)send_buf,data_len);
    msg->data[2] = xor_c;

    g_send_para.send_len = data_len + 1;
}

Ouint16 fpga_manage::load_write_reg_cmd_create(Ouint8 port,Ouint8 card_index, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf,bool smart_net)
{
    Ouint8 xor_c;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    if(smart_net){
        //msg->dstAddr = 0x0ffe | ((port % 4) << 12);
        msg->dstAddr = 0x0fff; //广播
    }else{
        msg->dstAddr = 0x0000 | ((port % 4) << 12) | card_index;
    }

    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = 0;
    msg->reserved1 = 0;
    msg->cmd = 0xa0;

    for(int i = 0 ; i < data_len ; i++){
        msg->data[i] = buf[i];
    }

    xor_c = Utils::BCC((Ouint8 *)send_buf,(10 + data_len));

    msg->data[data_len] = xor_c;

    g_send_para.send_len = data_len + 1 + 10;
    return (data_len + 1 + 10);
}



Ouint16 fpga_manage::load_write_user_defined_cmd_create(Ouint8 port,Ouint8 card_index, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf,bool smart_net)
{
    Ouint8 xor_c;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    if(smart_net){
        //msg->dstAddr = 0x0ffe | ((port % 4) << 12);
        msg->dstAddr = 0x0fff; //广播
    }else{
        msg->dstAddr = 0x0000 | ((port % 4) << 12) | card_index;
    }
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = 0;
    msg->reserved1 = 0;
    // msg->cmd = buf[i];


    for(int i = 0 ; i < data_len ; i++){
        ((Ouint8 *)(&msg->cmd))[i] = buf[i];
    }

    xor_c = Utils::BCC((Ouint8 *)send_buf,(9 + data_len));

    ((Ouint8 *)(&msg->cmd))[data_len] = xor_c;

    g_send_para.send_len = data_len + 1 + 9;
    return (data_len + 1 + 9);
}


Ouint16 fpga_manage::rcv_reconfig_cmd_create(Ouint8 port, Ouint8 card_index, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf/*,bool smart_net*/)
{
    Ouint8 xor_c;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;
    //if(smart_net){
    //msg->dstAddr = 0x0ffe | ((port % 4) << 12);
    //    msg->dstAddr = 0x0fff; //广播
    //}else{
    msg->dstAddr = 0x0000 | ((port % 4) << 12) | card_index;
    //}
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = (port + 1);
    msg->reserved1 = 0;
    msg->cmd = 0x84;

    for(int i = 0 ; i < data_len ; i++){
        msg->data[i] = buf[i];
    }

    xor_c = Utils::BCC((Ouint8 *)send_buf,data_len + 10);
    msg->data[data_len] = xor_c;

    g_send_para.send_len = data_len + 1 + 10;


    return (data_len + 1 + 10);
}


Ouint16 fpga_manage::load_search_rxc_cmd_create(Ouint8 port, Ouint8 *buf, Ouint16 data_len, Ouint8 *send_buf)
{
    Ouint8 xor_c;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    msg->dstAddr = 0x0ffe | ((port % 4) << 12);
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = (port+1);
    msg->reserved1 = 0;
    msg->cmd = CMD_SEARCH_GROUP;


    for(int i = 0 ; i < data_len ; i++){
        msg->data[i] = buf[i];
    }

    xor_c = Utils::BCC((Ouint8 *)send_buf,(10 + data_len));
    msg->data[data_len] = xor_c;


    g_send_para.send_len = data_len + 1 + 10;
    return (data_len + 1 + 10);
}



Ouint16 fpga_manage::save_para2flash_cmd_create(Ouint8 port, Ouint8 card_index , Ouint8 *send_buf, bool smart_net)
{
    Ouint8 xor_c;
    Ouint16 data_len;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    if(smart_net){
        //msg->dstAddr = 0x0ffe | ((port % 4) << 12);
        msg->dstAddr = 0x0fff; //广播
    }else{
        msg->dstAddr = 0x0000 | ((port % 4) << 12) | card_index;
    }


    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = 0;
    msg->reserved1 = 0;
    msg->cmd = 0x81;
    msg->data[0] = 0xff;
    msg->data[1] = 0;

    data_len = 12;//!<10+2

    xor_c = Utils::BCC((Ouint8 *)send_buf,data_len);
    msg->data[2] = xor_c;

    g_send_para.send_len = data_len + 1;
    return (data_len + 1);
}




void fpga_manage::mapping_enable_cmd_create(Ouint8 port,Ouint8 *send_buf)
{
    Ouint8 xor_c;
    Ouint16 data_len;
    PhyData_Type *msg;

    msg = (PhyData_Type *)send_buf;

    msg->dstAddr = 0x0fff;//广播
    //msg->dstAddr = 0x0ffe | ((port % 4) << 12);
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x67;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = port + 1;
    msg->reserved1 = 0;
    msg->cmd = 0xa0;


    msg->data[0] = 0x03;
    msg->data[1] = 0x0f;
    msg->data[2] = 0x01;
    msg->data[3] = g_send_para.offset;


    data_len = 14;//!<10+4

    xor_c = Utils::BCC((Ouint8 *)send_buf,data_len);
    msg->data[4] = xor_c;

    g_send_para.send_len = data_len + 1;
}

Ouint8 fpga_manage::get_operate_deal_para(SCAN_PARA *scan_para,Ouint8 index)
{
    int offset ;
    Ouint8 operate_buf[22];
    FILE* file_onbon = NULL;

    if(index >= g_load_scan_para.ConfigRcvTimes)
    {
        return 1;
    }


    string file_path ="/mnt/usb1/" ;
    Utils::_file_deal_mutex.lock();
    file_onbon = fopen(file_path.c_str(), "rb");
    if(file_onbon == NULL)
    {
        BX_printf("\n NO bxfile!!! \n");
        Utils::_file_deal_mutex.unlock();
        return 1;
    }
    offset = index * 22 + 4;
    fseek(file_onbon,offset,SEEK_SET) ;

    fread(operate_buf, 1, 22, file_onbon);
    fclose(file_onbon);
    Utils::_file_deal_mutex.unlock();

    scan_para->operation = operate_buf[0];
    scan_para->target = operate_buf[1];
    scan_para->targetAddr = SPLIT_8_to_32_LITTLE(operate_buf,2);
    scan_para->targetAddroffset = SPLIT_8_to_32_LITTLE(operate_buf,6);
    scan_para->dataLen = SPLIT_8_to_32_LITTLE(operate_buf,10);
    scan_para->dataOffset = SPLIT_8_to_32_LITTLE(operate_buf,14);
    scan_para->timeout = SPLIT_8_to_32_LITTLE(operate_buf,18) / 10 ;

    return 0;
}



Ouint8 fpga_manage::load_rcv_xy_operate(string files_rcv, Ouint32 offset, bool smart_net)
{

    return 0;
}












void fpga_manage::save_para_deal(void)
{
    Ouint8 send_buf[13];
    Ouint8 port_num;
    Ouint8 sel_fpga;

    if(pc_cmd_valid){

        if(Utils::getTimeSpace(pc_cmd_time)>SEARCH_ORDER_DELAY){
            pc_cmd_valid = 0;
            g_netport_recored=0;
        }
        g_change.sys_search_check_time = G_timeTicks;
        g_send_para.timeticks = G_timeTicks;
        return;
    }

    switch (g_send_para.state) {
    case 0:
        g_send_para.port = 0;//line_type.port;
        g_send_para.state = 1;
        BX_printf("\n start send save para!!! \n");
        break;
    case 1:

        if(g_send_para.port < g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
            g_send_para.card_num = get_port_card_num(g_send_para.port);
            if(g_send_para.card_num == 0){
                g_send_para.port++;
                BX_printf("\n no card to send save para!!! \n");
            }else{
                g_send_para.state = 2;
                BX_printf("\n send rcv card port : %d,%d!!! \n",g_send_para.port,g_send_para.card_num);
            }
        }else{

            g_send_para.state = 4;
        }


        break;
    case 2:

        port_num = g_send_para.port;
        if(port_num < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
            sel_fpga = FPGA_MASTER_VBYONE1;
        }else if(port_num < g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
            sel_fpga = FPGA_MASTER_VBYONE2;
            port_num = port_num - g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;
        }

        save_para_cmd_create(send_buf,port_num);

        Send_to_port(send_buf,sizeof(send_buf),port_num,sel_fpga);

        //g_smartmapping->sig_qround_bar_update( g_send_para.port / ( g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM+ 1) *100);

        g_send_para.port++;

        g_change.sys_record_second = 0;
        g_change.sys_search_check_time = G_timeTicks;

        g_send_para.timeticks = G_timeTicks;
        g_send_para.state = 3;
        break;
    case 3:
        if(g_send_para.rcv_back == 1){
            g_send_para.rcv_back = 0;
            g_send_para.state = 1;
            BX_printf("\n rcv message back!!! \n");
        }
        if(Utils::getTimeSpace(g_send_para.timeticks) > 1200 + g_send_para.card_num * 100){
            g_send_para.state = 1;
            BX_printf("\n timeout!!! \n");
        }

        if(Utils::getTimeSpace(g_change.sys_search_check_time) > 100){
            g_change.sys_record_second++;

            if(g_change.sys_record_second >= 100){
                g_change.sys_record_second = 1;

            }
            g_change.sys_search_check_time = G_timeTicks;
            //g_smartmapping->sig_qround_bar_update( g_change.sys_record_second );
        }

        break;
    case 4:
        g_send_para.state = 9;//0;
        //g_smartmapping->sig_qround_bar_update( 95 );
        BX_printf("\n send save para over!!! \n");
        g_send_para.timeticks = G_timeTicks;
        break;
    case 9:
        //回包太快了，造成界面来不及看
        //delay 1s
        if(Utils::getTimeSpace(g_send_para.timeticks) > 200){
            //g_smartmapping->sig_qround_bar_update( 100 );
            g_send_para.state = 0;
            g_send_para.type = 0;
        }
        break;
    default:
        break;
    }
}


void fpga_manage::mapping_enable_deal(void)
{
    Ouint8 send_buf[15];
    Ouint8 port_num;
    Ouint8 sel_fpga;

    if(pc_cmd_valid){

        if(Utils::getTimeSpace(pc_cmd_time)>SEARCH_ORDER_DELAY){
            pc_cmd_valid = 0;
            g_netport_recored=0;
        }
        g_change.sys_search_check_time = G_timeTicks;
        g_send_para.timeticks = G_timeTicks;
        return;
    }

    switch (g_send_para.state) {
    case 0:
        g_send_para.port = 0;//line_type.port;
        g_send_para.state = 1;
        BX_printf("\n start send save para!!! \n");
        break;
    case 1:
        if(g_send_para.port < g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
            g_send_para.card_num = get_port_card_num(g_send_para.port);
            if(g_send_para.card_num == 0){
                g_send_para.port++;
                BX_printf("\n no card to send mapping enable para!!! \n");
            }else{
                g_send_para.state = 2;
                BX_printf("\n send rcv card port : %d,card_num =%d!!! \n",g_send_para.port,g_send_para.card_num);
            }
        }else{

            g_send_para.state = 4;
        }

        break;
    case 2:
        port_num = g_send_para.port;
        if(port_num < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
            sel_fpga = FPGA_MASTER_VBYONE1;
        }else if(port_num < g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
            sel_fpga = FPGA_MASTER_VBYONE2;
            port_num = port_num - g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;
        }

        mapping_enable_cmd_create(port_num,send_buf);
        Send_to_port(send_buf,sizeof(send_buf),port_num,sel_fpga);

        //g_smartmapping->sig_qround_bar_update( g_send_para.port / ( g_Global->OVP_CONTROL_OUT_NUM*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM+ 1) *100);

        g_send_para.port++;

        g_change.sys_record_second = 0;
        g_change.sys_search_check_time = G_timeTicks;

        g_send_para.timeticks = G_timeTicks;
        g_send_para.state = 3;

        break;
    case 3:
        if(g_send_para.rcv_back == 1){
            g_send_para.rcv_back = 0;
            g_send_para.state = 1;
            BX_printf("\n rcv message back!!! \n");
        }
        if(Utils::getTimeSpace(g_send_para.timeticks) > 1200){
            g_send_para.state = 1;
            BX_printf("\n timeout!!! \n");
        }

        if(Utils::getTimeSpace(g_change.sys_search_check_time) > 100){
            g_change.sys_record_second++;

            if(g_change.sys_record_second >= 100){
                g_change.sys_record_second = 1;

            }
            g_change.sys_search_check_time = G_timeTicks;
            //g_smartmapping->sig_qround_bar_update( g_change.sys_record_second );
        }
        break;
    case 4:
        g_send_para.state = 9;//0;
        //g_smartmapping->sig_qround_bar_update( 95 );
        BX_printf("\n send mapping over!!! \n");
        g_send_para.timeticks = G_timeTicks;
        BX_printf("\n send mapping para over!!! \n");
        break;
    case 9:
        //回包太快了，造成界面来不及看
        //delay 1s
        if(Utils::getTimeSpace(g_send_para.timeticks) > 200){
            //g_smartmapping->sig_qround_bar_update( 100 );
            g_send_para.state = 0;
            g_send_para.type = 0;
        }
    default:
        break;
    }
}










//fun
/*!
* @brief  power_up_fpga_start()  FPGA init when power on or reset
* @param 	NONE
* @return	NONE
* @note
*/
void fpga_manage::power_up_fpga_start(Ouint8 flag,Ouint8 sel_fpag)
{

 #if 1
        if( (MCU_REG_func[sel_fpag][FPGA_INIT_OK] == 0x03)&&(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S7)&&
                (MCU_REG_func[sel_fpag][FPGA_INIT_OK] == 0x03)//||
                //(rst_chip.fpga1_flag==1)&&(sel_fpag==0) ||(rst_chip.fpga2_flag==1)&&(sel_fpag==1)
                ){
            return ;
        }
    //}
#endif
#if 0

    //setGpioHigLow(2, 30, 1);
    //setGpioHigLow(3, 10, 1);
    setGpioHigLow(3, 20, 1);

    sleep(1);

    //setGpioHigLow(2, 30, 0);
    //setGpioHigLow(3, 10, 0);
    setGpioHigLow(3, 20, 0);
    sleep(1);

    return;
#endif

    //read_from_register(FPGA_BYTE3_REG,sel_fpag);//ver-year
    //read_from_register(FPGA_BYTE2_REG,sel_fpag);//ver-month
    //read_from_register(FPGA_BYTE1_REG,sel_fpag);//ver-date
    //read_from_register(FPGA_BYTE0_REG,sel_fpag);//ver-fuc
    //printf("\n\n fpag[%d]_ver_year = %#x %#x\n\n",sel_fpag+1,MCU_REG_func[sel_fpag][FPGA_BYTE3_REG],MCU_REG_func[sel_fpag][FPGA_BYTE2_REG]) ;
    //BX_printf("\n\n fpag[%d]_ver_date = %#x %#x\n\n",sel_fpag+1,MCU_REG_func[sel_fpag][FPGA_BYTE1_REG],MCU_REG_func[sel_fpag][FPGA_BYTE0_REG]) ;
    //sleep(1);
    //return;


    //do{
    //if(G_timeTicks - g_change.sys_fpga_delay_time > wait_fpga_communite_time){//默认60
    //if(Utils::getTimeSpace(g_change.sys_fpga_ret_time[sel_fpag]) > 30){
        //if(G_timeTicks - g_change.sys_fpga_ret_time[sel_fpag] > 10){
        //BX_printf("\n year: %d \n",MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]) ;
        if( !( (MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]>=FPGA_VER_START_YEAR)&&(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]<=FPGA_VER_END_YEAR) )  )
        {
            /*for( i=0;i<8;i++){
                        flash_uid[i] = 0x00;

                    }*/
            /*
                    if(sel_fpag == FPGA_MASTER_VBYONE1){
                        p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE1,flash_uid);
                    }else{
                        p_fpga_manage->p_fpga_drv->FPGA_SPI_FLASH_SSTF016B_RD_UID(FPGA_FLASH_VBYONE2,flash_uid);
                    }
*/

            //read ver
            string version = "19010100";
            read_from_register(FPGA_BYTE3_REG,sel_fpag);//ver-year
            read_from_register(FPGA_BYTE2_REG,sel_fpag);//ver-month
            read_from_register(FPGA_BYTE1_REG,sel_fpag);//ver-date
            read_from_register(FPGA_BYTE0_REG,sel_fpag);//ver-fuc
            read_from_register(FPGA_HARD_PCB_VERSION,sel_fpag);//!<功能号
            fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S1;
            fpga_init_error[sel_fpag] = 0x00;
            //                    MCU_REG_func[sel_fpag][FPGA_HARD_PCB_VERSION]=11;

            Oint32 year = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE3_REG]);
            Oint32 month = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE2_REG]);
            Oint32 date = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE1_REG]);
            Oint32 fuc = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE0_REG]);
            version = Utils::intToString(year,2) + Utils::intToString(month,2) + Utils::intToString(date,2) + Utils::intToString(fuc,2);
            // ConfigSetString("fpgaversion", version, CONFIG_BOTH, 0);

            BX_printf("\n\n fpag[%d]_ver_year = %#x %#x\n\n",sel_fpag+1,MCU_REG_func[sel_fpag][FPGA_BYTE3_REG],MCU_REG_func[sel_fpag][FPGA_BYTE2_REG]) ;
            BX_printf("\n\n fpag[%d]_ver_date = %#x %#x\n\n",sel_fpag+1,MCU_REG_func[sel_fpag][FPGA_BYTE1_REG],MCU_REG_func[sel_fpag][FPGA_BYTE0_REG]) ;
            sleep(1);


            //                    BX_printf("\n\n flash_uid = %#x,%#x,%#x,%#x,%#x,%#x,%#x,%#x\,sel:%d\n\n",flash_uid[0],flash_uid[1],flash_uid[2],flash_uid[3],
            //                              flash_uid[4],flash_uid[5],flash_uid[6],flash_uid[7],sel_fpag) ;
            //                    return;

            //                    if(onbonsource::p_onbon_source->g_si5338_ic_valid == 0){
            //                        BX_printf("\n now start to init s5388 \n") ;
            //                        onbonsource::p_onbon_source->si5338_config_init();
            //                        onbonsource::p_onbon_source->si5338_write_config_data_to_ram();
            //                    }
            // return ;
            //                    g_RAM_MCU_PARA[VERF1_YEAR+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG])+2000;
            //                    g_RAM_MCU_PARA[VERF1_MONH+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE2_REG])/10;
            //                    g_RAM_MCU_PARA[VERF1_MONL+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE2_REG])%10;
            //                    g_RAM_MCU_PARA[VERF1_DAYH+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE1_REG])/10;
            //                    g_RAM_MCU_PARA[VERF1_DAYL+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE1_REG])%10;
            //                    //功能号以16进制来表示  其它按10进制来表示
            //                    g_RAM_MCU_PARA[VERF1_FUNH+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE0_REG])/10;
            //                    g_RAM_MCU_PARA[VERF1_FUNL+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_BYTE0_REG])%10;
            //                    g_RAM_MCU_PARA[VERF1_SOFTH+sel_fpag*10]=0;
            //                    g_RAM_MCU_PARA[VERF1_SOFTL+sel_fpag*10]=0;
            //                    g_RAM_MCU_PARA[VERF1_HARD+sel_fpag*10]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_HARD_PCB_VERSION]);//10;

            //                     if((sel_fpag==FPGA_MASTER_VBYONE1)&&(MCU_REG_func[FPGA_MASTER_NEAR_VBYEON][FPGA_BYTE3_REG]>=0x19)
            //                        &&(MCU_REG_func[FPGA_MASTER_NEAR_VBYEON][FPGA_BYTE3_REG]<=0x23) ){
            //                        SCREEN_fpgactrl_status(DSP_RESET_ING);
            //                        FPGA1_RST_H();
            //                    }
        }
#if 1
        else if((fpga_init_step[sel_fpag] >= FPGA_VBO_INIT_S1)&&(fpga_init_step[sel_fpag] <= FPGA_VBO_INIT_S5)&&
                (MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]>=FPGA_VER_START_YEAR)&&(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]<=FPGA_VER_END_YEAR)&&
                (MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]>=FPGA_VER_START_YEAR)&&(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]<=FPGA_VER_END_YEAR))
        {
            if(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S1){
                BX_printf("\n +++++++++++++++++++++FPGA[%d]_VBO_INIT_S1++++++++++++++++++++++++ !!!\n",sel_fpag+1) ;
                write_to_register(/*0x03*/FPGA_STATE_REG_03,0x40,0x40,sel_fpag);//1
                fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S2;
            }else if(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S2){
                BX_printf("\n +++++++++++++++++++++FPGA[%d]_VBO_INIT_S2++++++++++++++++++++++++ !!!\n",sel_fpag+1) ;
                read_from_register(FPGA_STATE0_REG,sel_fpag);
                if( (MCU_REG_func[sel_fpag][FPGA_STATE0_REG]&0x08) == 0x08){
                    //error
                    BX_printf("\n +++++++++++++++++FPGA[[%d]]_VBO_INIT_S2 error!!!++++++++++++++++\n",sel_fpag+1) ;
                    fpga_init_error[sel_fpag]++;
                    if(fpga_init_error[sel_fpag] >= 5/*1500*/){//about 15s 15*1000/10=1500
                        fpga_init_rst_times[sel_fpag]++;

                        if(fpga_init_rst_times[sel_fpag] >= 0x03){
                            fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S3;
                        }else{
                            BX_printf("\n +++++++++++++++++FPGA[%d]_VBO_INIT_S2 reset!!!++++++++++++++++\n",sel_fpag+1) ;
                            if(sel_fpag == FPGA_MASTER_VBYONE1){
                                fpga1_rst_flag = true;
                                fpga1_rst_ticks = G_timeTicks;
                                //setGpioHigLow(3, 10, 0) ;
                            }
                        }
                    }

                }else{
                    fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S3;
                }
            }else if(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S3){
                BX_printf("\n +++++++++++++++++++++FPGA[%d]_VBO_INIT_S3++++++++++++++++++++++++ !!!\n",sel_fpag+1) ;
                write_to_register(/*0x03*/FPGA_STATE_REG_03,0x80,0x80,sel_fpag);//1
                fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S5;//FPGA_VBO_INIT_S4;
                fpga_init_error[sel_fpag] = 0x00;
                fpga_init_rst_times[sel_fpag] = 0x00;

            }/*else if(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S4){
                        read_from_register(FPGA_VBO_REG,sel_fpag);
                        if( (MCU_REG_func[sel_fpag][FPGA_VBO_REG]&0x1C) == 0x1C){
                            fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S5;
                            fpga_init_rst_times[sel_fpag] = 0x00;
                            //error

                        }else{
                            //BX_printf("\n +++++++++++++++++FPGA_VBO_INIT_S4 error!!!++++++++++++++++\n") ;
                            fpga_init_error[sel_fpag]++;
                            if(fpga_init_error[sel_fpag] > 1500){
                                fpga_init_rst_times[sel_fpag] ++;

                                if(fpga_init_rst_times[sel_fpag] >= 0x03){
                                    fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S5;
                                    fpga_init_error[sel_fpag] = 0x00;
                                    fpga_init_rst_times[sel_fpag] = 0x00;

                                }else{
                                    //BX_printf("\n +++++++++++++++++FPGA_VBO_INIT_S4 reset!!!++++++++++++++++\n") ;
                                    if(sel_fpag == FPGA_MASTER_VBYONE1){
                                        fpga1_rst_flag = true;
                                        fpga1_rst_ticks = G_timeTicks;
                                        setGpioHigLow(3, 10, 0) ;
                                    }else{
                                        fpga2_rst_flag = true;
                                        fpga2_rst_ticks = G_timeTicks;
                                        *(unsigned short *)(addr_gpio48) = GPIO48_CONTENT_L;
                                    }
                                }
                            }

                        }
                    }*/else if((fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S5)){
                BX_printf("\n +++++++++++++++++++++FPGA[%d]_VBO_INIT_S5++++++++++++++++++++++++ !!!\n",sel_fpag+1) ;
                read_from_register(FPGA_STATE0_REG,sel_fpag);
                if( (MCU_REG_func[sel_fpag][FPGA_STATE0_REG]&0x10) == 0x10){
                    fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S6;
                    fpga_init_rst_times[sel_fpag] = 0x00;
                    //VBYONE_NO_DIV_MODE
                    //SCREEN_fpgactrl_status(VBYONE_NO_DIV_MODE);
                    write_to_register(FPGA_CLEAR_REG,0x01,0x00,sel_fpag);

                }else{
                    BX_printf("\n +++++++++++++++++FPGA[%d]_VBO_INIT_S5 error!!!++++++++++++++++\n",sel_fpag+1) ;
                    fpga_init_error[sel_fpag]++;
                    if(fpga_init_error[sel_fpag] > 5/*1500*/){
                        fpga_init_rst_times[sel_fpag] ++;

                        if(fpga_init_rst_times[sel_fpag] >= 0x03){
                            fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S6;
                        }
                    }

                }
            }
        }
        else
#endif


            if((fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S6)&&(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]>=FPGA_VER_START_YEAR)&&(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]<=FPGA_VER_END_YEAR)&&
                    (MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]>=FPGA_VER_START_YEAR)&&(MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]<=FPGA_VER_END_YEAR))
            {
                BX_printf("\n +++++++++++++++++++++FPGA[%d]_VBO_INIT_S6++++++++++++++++++++++++ !!!\n",sel_fpag+1) ;
                //                    if(g_RAM_IN_MCU[MCU_PARA3_BITS_INFO]&SET_BIT(FPGA_REST_BIT_OK)){
                //                        SCREEN_fpgactrl_status(DSP_RESET_OK_2);
                //                        g_RAM_IN_MCU[MCU_PARA3_BITS_INFO]&=CLEAR_BIT(FPGA_REST_BIT_OK);
                //                    }else{
                //                        SCREEN_fpgactrl_status(DSP_RESET_ING_1); //通知FPGA1异常
                //                    }

                //                    //g_change.sys_FPGA_init_flag = 0;
                //                    //正常初始化标记
                //                    sel_fpag=FPGA_MASTER_VBYONE1;
                //                    MCU_REG_func[sel_fpag][FPGA_INIT_OK] = 0x03;

                //                    sel_fpag=FPGA_MASTER_VBYONE2;
                //                    MCU_REG_func[sel_fpag][FPGA_INIT_OK] = 0x03;

                //                    sel_fpag=FPGA_MASTER_VBYONE2;
                //                    read_from_register(FPGA_HARD_PCB_VERSION,sel_fpag);//读取FPGA PCB版本号
                //                    g_RAM_MCU_PARA[VERF1_HARD]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_HARD_PCB_VERSION]);//10;

                //                    //表示网口输出时
                //#ifdef OUTPUT_LEDNET
                //                    if(sel_fpag == FPGA_MASTER_VBYONE1){
                //                        //寄存器0x03 bit6 表示FPGA的V-BY-ONE总线接入
                //                        write_to_register(0x03,0x40,0x40,sel_fpag);
                //                        //寄存器0x03 bit7 表示FPGA的V-BY-ONE总线识别成功
                //                        write_to_register(0x03,0x80,0x00,sel_fpag);
                //                    }
                //add by


                //read_from_register(0x03,sel_fpag);
                //BX_printf("\n\n before 0x03 = %#x +++++++++++++++++++++++++++++++++++++++++++\n\n",MCU_REG_func[sel_fpag][0x03]) ;
                //write_to_register(0x03,0xff,0x00,sel_fpag);//0x03 default value is 0xff.

                //                    write_to_register(0x03,0xC0,0xC0,sel_fpag);//1//    if(flag){
                //#if 0
                //        if((g_init_dsp_1==9)&&((g_RAM_IN_MCU[BOOT_UP_INIT_STATE]& SET_BIT(BOOT_UP_INIT_OVER)))){
                //            fpga_restart_config();
                //            g_init_dsp_1=100;
                //            return ;
                //        }
                //#endif

                //        if( (MCU_REG_func[sel_fpag][FPGA_INIT_OK] == 0x03)&&(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S7)&&
                //                (MCU_REG_func[sel_fpag][FPGA_INIT_OK] == 0x03)//||
                //                //(rst_chip.fpga1_flag==1)&&(sel_fpag==0) ||(rst_chip.fpga2_flag==1)&&(sel_fpag==1)
                //                ){
                //            return ;
                //        }
                //    }

                //read_from_register(0x03,sel_fpag);
                //BX_printf("\n\n next 0x03 = %#x +++++++++++++++++++++++++++++++++++\n\n",MCU_REG_func[sel_fpag][0x03]) ;


                //                    BX_printf("\n LED_INFO_OCH_W=%d,LED_INFO_OCH_H=%d \n",SPLIT_8_to_16(p_ram0_u8,LED_INFO_OCH_W),SPLIT_8_to_16(p_ram0_u8,LED_INFO_OCH_H)) ;
#if 0//!defined(SUPPORT_OCH_8K)
                if((SPLIT_8_to_16(p_ram0_u8,LED_INFO_OCH_MODE) & 0x01)  == 0x00){

                    SCREEN_fpgactrl_status(VBYONE_NO_DIV_MODE);

                }
                else
#endif
                {

                    //SCREEN_fpgactrl_status(VBYONE_SPLICE_MODE);
                    write_to_register(FPGA_CLEAR_REG,0x01,0x01,sel_fpag);
                }

                MCU_REG_func[sel_fpag][FPGA_INIT_OK] = 0x03;
                //fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S7;


                fpgainit(sel_fpag);
                //write_to_register(0x03,0x20,0x20,sel_fpag);//!<调整为先置1在初始化参数

                //read_from_register(0x03,sel_fpag);
                // BX_printf("\n\n after 0x03 = %#x +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\n",MCU_REG_func[sel_fpag][0x03]) ;


                //                    //由于M2D 默认LCD开启，不再要求MCU来控制；输出稳定由后后级来确认
                //                    if(flag==0){
                //                        //禁止LCD总线输入 由于单独升级FPGA时 不知道DSP是否需要升级  则默认升级 FGPA时 不再禁止
                //                        //write_to_register(0x03,0x20,0x00);
                //                        SCREEN_fpgactrl_status(DISENABLE_LCD);
                //                    }else{
                //                        //使能LCD总线输入  默认FPGA 关闭LCD总线
                //                        //write_to_register(0x03,0x20,0x20);
                //                        //write_to_register(0x03,0x20,0x20);
                //                        //SCREEN_fpgactrl_status(ENABLE_LCD);
                //                    }
                //                    write_to_register(0x03,0x20,0x20,sel_fpag);
                //                    write_to_register(0x03,0x20,0x20,sel_fpag);


                //                    sel_fpag=FPGA_MASTER_VBYONE2;

                //                    read_from_register(FPGA_HARD_PCB_VERSION,sel_fpag);//读取FPGA PCB版本号
                //                    g_RAM_MCU_PARA[VERF1_HARD]=BCD_to_HEC(MCU_REG_func[sel_fpag][FPGA_HARD_PCB_VERSION]);//10;

                //                    fpgainit(sel_fpag);

                //                    write_to_register(0x03,0x20,0x20,sel_fpag);
                //                    write_to_register(0x03,0x20,0x20,sel_fpag);


                //#endif

                //                    g_init_dsp_ticks = G_timeTicks;
                //                    if(g_init_dsp_1==0){
                //                        g_init_dsp_1=1;
                //                    }


                MCU_REG_func[sel_fpag][FPGA_INIT_OK] = 0x03;
                fpga_init_step[sel_fpag] = FPGA_VBO_INIT_S7;
                //check_fpga_phy_status[sel_fpag] = 0x00;
                //check_fpga_phy_ticks[sel_fpag] = G_timeTicks;
                //MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] = 0x03;
                //MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] = 0x03;

#if ENABLE_OUT2_DELAY_
                if(sel_fpag == FPGA_MASTER_VBYONE1){
                    if(g_change.sys_power_init == 0){
                        g_change.sys_power_init = 1;
                        g_change.sys_fpga_check_init_ticks = G_timeTicks;
                    }


                }
#endif
                return ;
            }

        g_change.sys_fpga_ret_time[sel_fpag] = G_timeTicks;
    //}
}


#if 1
void fpga_manage::power_up_check_fpga_status(Ouint8 sel_fpag)
{
    Ouint32 dvi_w,dvi_h,dvi_f;
    Ouint32 /*splice,*/led_w,led_h;
    Ouint16 /*width,height,freq,source_id,*/flag;
    //Ouint8 * p_ram0_u8 =  OvpRamPara::p_ovprampara_config->ovp_ram.ovpG3ram0;

#if 0

#else
    if((MCU_REG_func[sel_fpag][FPGA_INIT_OK] == 0x03)&&(fpga_init_step[sel_fpag] == FPGA_VBO_INIT_S7)){
        if((check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_START)&&\
                (Utils::getTimeSpace(check_fpga_phy_ticks[sel_fpag] ) > 10)){

            read_from_register(FPGA_STATE0_REG,sel_fpag);

            if((MCU_REG_func[sel_fpag][FPGA_STATE0_REG]& 0x80) == 0x80){
                check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S9;//FPGA_PHY_INIT_S1;
            }else{

                if(check_frame_stable[sel_fpag] >= 20 + check_frame_reset[sel_fpag]*20){
                    if(check_frame_reset[sel_fpag] > 100){
                        check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S9;//FPGA_PHY_INIT_S1;

                    }else{
                        check_frame_reset[sel_fpag]++;

                    }


                    if(sel_fpag == FPGA_MASTER_VBYONE1){
                        fpga1_rst_flag = true;
                        fpga1_rst_ticks = G_timeTicks;
                        setGpioHigLow(3, 10, 0) ;

                    }

                    fpga_init_step[sel_fpag] = FFPA_PHY_INIT_WAIT;


                }else{
                    check_frame_stable[sel_fpag]++;
                }

            }
            check_fpga_phy_ticks[sel_fpag] = G_timeTicks;
            BX_printf("\n fpga%d************%d\n",sel_fpag+1,MCU_REG_func[sel_fpag][FPGA_STATE0_REG]) ;


        }else if((check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S9)&&\
                 (Utils::getTimeSpace(check_fpga_phy_ticks[sel_fpag] ) > 70)){

            flag = 0;
            /*for(source_id =0 ; source_id < 6 ; source_id++){
                    width = SPLIT_8_to_16(p_ram0_u8,INPUT1_1_SOURCE_RAM_W+(INPUT1_2_SOURCE_RAM_W - INPUT1_1_SOURCE_RAM_W)*source_id);
                    height = SPLIT_8_to_16(p_ram0_u8,INPUT1_1_SOURCE_RAM_H+(INPUT1_2_SOURCE_RAM_W - INPUT1_1_SOURCE_RAM_W)*source_id);
                    freq = SPLIT_8_to_16(p_ram0_u8,INPUT1_1_SOURCE_RAM_F+(INPUT1_2_SOURCE_RAM_W - INPUT1_1_SOURCE_RAM_W)*source_id);

                    if(!(width == 0 || height == 0 || freq == 0)){
                           flag = 1;
                    }
                }*/
            flag = 1;

            if(flag){
                read_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][0x74],0x74, 8,PARA_RAM,sel_fpag);

                dvi_w = MCU_RAM_PARA_func[sel_fpag][0x74] | (MCU_RAM_PARA_func[sel_fpag][0x75]<<8);
                dvi_h = MCU_RAM_PARA_func[sel_fpag][0x76] | (MCU_RAM_PARA_func[sel_fpag][0x77]<<8);
                dvi_f = MCU_RAM_PARA_func[sel_fpag][0x78] | (MCU_RAM_PARA_func[sel_fpag][0x79]<<8) | (MCU_RAM_PARA_func[sel_fpag][0x7a]<<16) | (MCU_RAM_PARA_func[sel_fpag][0x7b]<<24);

                // splice = SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_SPLICE);
                //led_w = SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_WIDTH);
                led_w = 4000;
                led_h = 1000;
                //led_h = SPLIT_8_to_16(p_ram0_u8,LED_INFO_LED_HEIGHT);


                //50-70Hz ok(20ns)

                //if(dvi_w < led_w/2 || dvi_h <led_h/2 || (dvi_f >= 1000000) || (dvi_f <=714285)){
                    //BX_printf("\nfpag%d.......error(%d,%d,%d)................\n",sel_fpag+1,dvi_w,dvi_h,dvi_f)

                //}else
                {
                    //由于在设置LED屏参时有概率会出现一直30Hz闪屏的情况，所以根据虎平的建议，加上这个，来进行判断
                    //更新后效果更差
                    write_to_register(FPGA_RAM_REG_02,0x01,0x01,sel_fpag);//update reg
                    write_to_register(FPGA_RAM_REG_02,0x01,0x01,sel_fpag);//update reg
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S1;
                    BX_printf("\nfpag%d.......ok(%d,%d,%d)  123................\n",sel_fpag+1,dvi_w,dvi_h,dvi_f)
                }

            }




            check_fpga_phy_ticks[sel_fpag] = G_timeTicks;

        }


        //执行
        else if(check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S1){
            write_to_register(FPGA_ALIGN_REG,0x01,0x01,sel_fpag);//更新寄存器
            BX_printf("\n --------------------start green align!!!!!!-----------------fpga%d-------------- \n",sel_fpag+1) ;
            check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S200;//FPGA_PHY_INIT_S2;
            g_change.sys_fpga_check_ticks[sel_fpag] = G_timeTicks;
            //#ifndef OVP_CONTROL_G16C
            //
            //内蒙有一台G24断电上电可能会花屏，这样处理后有效果，不再区分指定的型号
            //内家的一台G24断电上电有概率出现寄存器17 BIT1清不掉的情况，目前采用查询的方式。测试断上电未出现异常
            write_to_register(FPGA_CLEAR_REG,0x02,0x02,sel_fpag);

            BX_printf("\n --------------------check_fpga_singal_reset  0005-----------fpga%d-------------- \n",sel_fpag) ;
            //#endif
        }else if(check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S200){
            if(Utils::getTimeSpace(g_change.sys_fpga_check_ticks[sel_fpag]) > 5){
                read_from_register(FPGA_CLEAR_REG,sel_fpag);
                if(MCU_REG_func[sel_fpag][FPGA_CLEAR_REG]&0x02){
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S2;

                    BX_printf("\n --------------------check_fpga%d_singal_reset  0006-------------------------- \n",sel_fpag+1) ;
                }else{
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S1;

                    BX_printf("\n --------------------check_fpga%d_singal_reset  0007---------------------------- \n",sel_fpag+1) ;

                }
                g_change.sys_fpga_check_ticks[sel_fpag] = G_timeTicks;

            }
        }else if(check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S2){
            if(Utils::getTimeSpace(g_change.sys_fpga_check_ticks[sel_fpag]) > 20){
                read_from_register(FPGA_ALIGN_REG,sel_fpag);
                if( (MCU_REG_func[sel_fpag][FPGA_ALIGN_REG]&0x10) == 0x10){
                    green_check_ok[sel_fpag] = 1;
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S300;//FPGA_PHY_INIT_S3;

                    BX_printf("\n --------------------check_fpga[%d]_singal_reset  0008---------------------------- \n",sel_fpag+1) ;
                }else{
                    //BX_printf("\n --------------------green check error!!!!!! sel_fpga : %d---------------------- \n",sel_fpga) ;
                    /*if(sel_fpga == FPGA_MASTER_VBYONE1){
                                                fpga1_rst_flag = true;
                                                fpga1_rst_ticks = G_timeTicks;
                                                setGpioHigLow(3, 10, 0) ;
                                            }else{
                                                fpga2_rst_flag = true;
                                                fpga2_rst_ticks = G_timeTicks;
                                                *(unsigned short *)(addr_gpio48) = GPIO48_CONTENT_L;
                                            }
                                            check_fpga_phy_status[sel_fpga] = FPGA_PHY_INIT_START;*/
                    green_check_ok[sel_fpag] = 1;
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S300;//FPGA_PHY_INIT_S3;

                    BX_printf("\n --------------------check_fpga[%d]_singal_reset  0009---------------------------- \n",sel_fpag+1) ;
                }
            }
        }else if(check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S300){
            write_to_register(FPGA_CLEAR_REG,0x02,0x00,sel_fpag);
            check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S400;
            g_change.sys_fpga_check_ticks[sel_fpag] = G_timeTicks;


            //BX_printf("\n --------------------check_fpga%d_singal_reset  0010-------------------------- \n",sel_fpag+1) ;

        }else if(check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S400){
            //内家的一台G24断电上电有概率出现寄存器17 BIT1清不掉的情况，目前采用查询的方式。测试断上电未出现异常
            if(Utils::getTimeSpace(g_change.sys_fpga_check_ticks[sel_fpag]) > 5){
                read_from_register(FPGA_CLEAR_REG,sel_fpag);
                if(!(MCU_REG_func[sel_fpag][FPGA_CLEAR_REG]&0x02)){
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S3;
                    BX_printf("\n --------------------check_fpga%d_singal_reset  0011------------------------- \n",sel_fpag+1) ;
                }else{
                    check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S300;
                    BX_printf("\n --------------------check_fpga%d_singal_reset  0012------------------------- \n",sel_fpag+1) ;
                }
            }
        }
        else if(check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S3){

#if (defined OUTPUT_BOARD_2)
            if((green_check_ok[FPGA_MASTER_VBYONE1] == 1)&&(green_check_ok[FPGA_MASTER_VBYONE2] == 1)){
#else
            if(green_check_ok[sel_fpag] == 1){
#endif
                //#ifndef OVP_CONTROL_G16C
                //
                //内蒙有一台G24断电上电可能会花屏，这样处理后有效果，不再区分指定的型号
                //内家的一台G24断电上电有概率出现寄存器17 BIT1清不掉的情况，目前采用查询的方式。测试断上电未出现异常
                //write_to_register(FPGA_CLEAR_REG,0x02,0x00,sel_fpga);
                //#endif
                //BX_printf("\n --------------------RAM PARA reset!!!!!!---------------------- \n") ;
                write_to_register(FPGA_RAM_REG_02,0x01,0x01,sel_fpag);//更新寄存器
                BX_printf("\n --------------------enable LCD!!!!!!---------------------- \n") ;
                // write_to_register(/*0x03*/FPGA_STATE_REG_03,0x20,0x20,sel_fpga);//!<调整为先置1在初始化参数

                //pthread_mutex_lock(&c331_manage::p_c331_manage->m_deal_about_c331_mutex);
                g_force_bkcolor=0;     //bit0=强迫蓝屏
                //c331_manage::p_c331_manage->deal_about_c331 =1;
                //pthread_mutex_unlock(&c331_manage::p_c331_manage->m_deal_about_c331_mutex);

                check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S600;//FPGA_PHY_INIT_END;
                BX_printf("\n --------------------check_fpga%d_singal_reset  0013--------------------------- \n",sel_fpag+1) ;
            }

        }
        //执行
















        else  if((check_fpga_phy_status[sel_fpag] == /*FPGA_PHY_INIT_S3*/FPGA_PHY_INIT_S600)&&\
                 (Utils::getTimeSpace(check_fpga_phy_ticks[sel_fpag] ) > 50)){

            SCREEN_fpgactrl_status2(CHECK_FPGA_PHY_OK,sel_fpag);
            check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_S601;//FPGA_PHY_INIT_S4;
            write_to_register(FPGA_RAM_REG_02,0x01,0x01,sel_fpag);//update reg
            write_to_register(FPGA_RAM_REG_02,0x01,0x01,sel_fpag);//update reg
            BX_printf("\n power_up_check_fpga_status start to OK phy !!!\n") ;
            check_fpga_phy_ticks[sel_fpag] = G_timeTicks;

        }
        else  if((check_fpga_phy_status[sel_fpag] == FPGA_PHY_INIT_S601/*FPGA_PHY_INIT_S4*/)&&\
                 (Utils::getTimeSpace(check_fpga_phy_ticks[sel_fpag] ) > 50)){

            /*if(Timeout_flag & 0x01){
                Ouint8 overtime = 0;
                if(IT8563WE_Get(&read_time) == 0){
                    overtime = Check_TimeOut();
                    if(overtime)
                    {
                        SCREEN_fpgactrl_status2(SCREEN_BLACK,sel_fpag);
                        SCREEN_fpgactrl_status2(SCREEN_BLACK,sel_fpag);
                    }
                }
            }*/
            SCREEN_fpgactrl_status2(ENABLE_LCD,sel_fpag);
            // write_to_register(/*0x03*/FPGA_STATE_REG_03,0x20,0x20,sel_fpag);//!<调整为先置1在初始化参数
            check_fpga_phy_status[sel_fpag] = FPGA_PHY_INIT_END;// FPGA_PHY_INIT_S5;
            check_fpga_phy_ticks[sel_fpag] = G_timeTicks;
            BX_printf("\n power_up_check_fpga_status start to OK phy (%d)!!!\n",sel_fpag) ;
        }

    }

#endif


}




#endif


//fuc check irq
/*!
*  @brief	check_fpga_irq()
*  @param	none
*  @return	none
*  @note	none
*/
#if 0
int fpga_manage::check_fpga_irq(Ouint8 sel_fpag)
{
#if 1
    timeval tm;
    fd_set set, err_set;
    tm.tv_sec  = TIMEOUT_SEC;
    tm.tv_usec = 0;
    struct input_event input_mouse;
    //    FD_ZERO(&set);
    //    FD_SET(fpga_irq_vbyone_event_fd , &set);
    //    FD_ZERO(&err_set);
    //    FD_SET(fpga_irq_vbyone_event_fd, &err_set);

    memset(&input_mouse,0,sizeof(input_mouse)) ;

    //Oint32 result = select(fpga_irq_vbyone_event_fd+1,  NULL,  &set, &err_set, NULL);
    Oint32 result =1;
    if(result > 0){

        BX_printf(" \r\n check_fpga_irq in... \r\n") ;

        //    if(FD_ISSET(fpga_irq_vbyone_event_fd, &err_set))
        {
            //BX_printf("===FD_ISSET(check_fpga_irq, &err_set)=== \n");
            //Close();
            //         return -1;
        }

        // read(fpga_irq_vbyone_event_fd,&input_mouse,sonbon_test,gpio_keys_gpio_report_eventizeof(struct input_event )) ;

#if 1
        // if (FD_ISSET(fpga_irq_vbyone_event_fd, &set)){


        if(sizeof(struct input_event) ==  read(fpga_irq_vbyone_event_fd,&input_mouse,sizeof(struct input_event )) )
        {
            if(input_mouse.type == EV_KEY)
            {
                //BX_printf("\r\n===FD_ISSET(check_fpga_irq, &set)=== 000  \n") ;
                if(input_mouse.value == 1 || input_mouse.value == 1)
                {
                    BX_printf("\r\n===FD_ISSET(check_fpga_irq, &set)=== code = %d ,value = %d \n",input_mouse.code,input_mouse.value) ;


                }else{

                }



            }

            //
        }


        // }
#endif

    }

#else



#endif
}
#endif





Ouint8 fpga_manage::Dealwith1_PC_to_eth(Ouint32 len, Ouint8 *data)
{
    Ouint16 data_len,addr;
    Ouint16 port_num=0;
    //    PHY_TX* phy_tx;
    Ouint16 DstAddr;
    Ouint8 valid = 1,sel_flag=FPGA_MASTER_VBYONE1;
#if PC_WIFI_LAN_UART_SAME
    //    phy_tx = &g_phy_deal.phy_tx[FPGA_SPI];
#else
    //这个可能有问题 暂放
    phy_tx = &g_phy_deal.phy_tx[WLAN_PC];
#endif


    DstAddr = (data[0] | (data[1]<<8));
    // phy_tx->send_len = len ;
    data_len = len;// phy_tx->send_len;

    // BX_printf("\n Dealwith1_PC_to_eth pc to fpga(src) len=%d ,type=%d\n",len ,data[FRAME_CONTROL_CLASS]) ;
    //    for(int i=0;i<len;i++){
    //        BX_printf(" %#x ",phy_tx->data[i]) ;
    //    }
    //    BX_printf("\n");





    if((data_len<RAM_MAX_LEN)){
        g_sync_netport_trans_mode=0;
        write_to_register(FPGA_CONTROL3_REG,0x0F,0x00,FPGA_MASTER_VBYONE1);//!<使能发送
        write_to_register(FPGA_CONTROL1_REG,0x0F,0x00,FPGA_MASTER_VBYONE1);//!<使能发送
#if (defined OUTPUT_BOARD_2)
        write_to_register(FPGA_CONTROL3_REG,0x0F,0x00,FPGA_MASTER_VBYONE2);//!<使能发送
        write_to_register(FPGA_CONTROL1_REG,0x0F,0x00,FPGA_MASTER_VBYONE2);//!<使能发送
#endif
        if((data[FRAME_CONTROL_CLASS] == CONTROL_CLASS_RCV||
            data[FRAME_CONTROL_CLASS] == CONTROL_CLASS_MULTCARD)||
                data[FRAME_CONTROL_CLASS] == CONTROL_CLASS_WILDCARD){
            if(data[FRAME_NETPORT] == 0xff){
                //发送给所有网口
                g_sync_netport_trans_mode=1;
#if 0
                //提到上面去，目前遇到一台G32运行10来个时后级接收卡查询不到，原因是无数据但是0x83寄存器异常造成通讯阻塞
                write_to_register(FPGA_CONTROL3_REG,0x0F,0x00,FPGA_MASTER_VBYONE1);//!<使能发送
                write_to_register(FPGA_CONTROL1_REG,0x0F,0x00,FPGA_MASTER_VBYONE1);//!<使能发送
#if (defined OUTPUT_BOARD_2)
                write_to_register(FPGA_CONTROL3_REG,0x0F,0x00,FPGA_MASTER_VBYONE2);//!<使能发送
                write_to_register(FPGA_CONTROL1_REG,0x0F,0x00,FPGA_MASTER_VBYONE2);//!<使能发送
#endif
#endif
                if(g_check_netport_trans_mode){
                    //如果上一帧并发并没有完成
                    //return ;
                    //valid=3;
                    g_check_netport_trans_mode=0; //并发操作完成
                    g_fpga_ack_statue = 0;
                    if(DstAddr == 0x0ffe){//数据流模式
                        g_dataflow_flag = 1;
                        /*g_netport_trans_ticks= 9*2*100*check_netport_card();
                         if(g_netport_trans_ticks==0){
                            g_netport_trans_ticks=3000;
                         }*/
                    }else{
                        g_dataflow_flag=0;
                        //g_netport_trans_ticks= 9*2*100+2*check_netport_card();
                    }
                    g_net_frame_seq= data[FRAME_SEQUENCE_NUMBER];
                    multi_port_send(data,data_len);
                }else{
                    g_check_netport_trans_mode=0; //并发操作完成
                    g_fpga_ack_statue = 0;
                    if(DstAddr == 0x0ffe){//数据流模式
                        g_dataflow_flag = 1;
                        /*g_netport_trans_ticks= 8*2*100*check_netport_card();
                         if(g_netport_trans_ticks==0){
                            g_netport_trans_ticks=2000;
                         }*/
                    }else{
                        g_dataflow_flag=0;
                        //g_netport_trans_ticks= 8*2*100+2*check_netport_card();
                    }
                    g_net_frame_seq= data[FRAME_SEQUENCE_NUMBER];
                    multi_port_send(data,data_len);

                }
                //if(valid){
                //透传过成
                //                     phy_tx->send_flag = PHY_S_INITIAL_FLAG;	                //!<发送完毕
                //                     phy_tx->send_num = 0;
                //                     phy_tx->send_state = PHY_S_INITIAL_STATE;

                //}
                //                 g_phy_deal.phy_rx[UART_PC].rcv_flag_ticks=G_timeTicks;//防止上次发送的命令接收了但是超时造成无效

                //                 g_phy_deal.phy_rx[UART_PC].rcv_flag_ticks=G_timeTicks;

            }else{
                //sel_flag = FPGA_MASTER_VBYONE1;//((phy_tx->data[FRAME_NETPORT]-1)/8);


                if(data[FRAME_NETPORT] > 0){
                    port_num = data[FRAME_NETPORT] - 1 ;//-8*sel_flag;//!<减一主要是程序里目前从0开始计数
#if (defined OUTPUT_BOARD_2)
                    if(port_num > g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM-1){
                        sel_flag = FPGA_MASTER_VBYONE2;
                        port_num = port_num - g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;
                    }
#endif
                }else{
                    sel_flag = FPGA_MASTER_VBYONE1;//0;
                    port_num = (DstAddr&0x3000)>>12 ;

                    BX_printf("FRAME_NETPORT : %d   port_num : %d\n",data[FRAME_NETPORT],port_num);
                }


                if(/*(port_num >= 0) && */(port_num < 0x20)){
                    addr = port_num % 4;
                    data[1] |= (addr << 4);
                    //!<因为替换的是0x00，这里直接把校验码异或一下就是新的校验码
                    data[data_len - 1] ^= (addr << 4);
                }


                //if(port_num > 0x1f){//最多支持32个
                //     port_num = (DstAddr & 0x3000)>>12;
                //}

                //                 BX_printf("\n Dealwith1_PC_to_eth pc to fpga(Send_to_port)port_num=%d \n",port_num) ;
                //                 for(int i=0;i<data_len;i++){
                //                     BX_printf(" %#x ",phy_tx->data[i]) ;
                //                 }
                //                 BX_printf("\n");


                Send_to_port(data,data_len,port_num,sel_flag);
                //if(valid){
                //透传过成
                //                    phy_tx->send_flag = PHY_S_INITIAL_FLAG;	                //!<发送完毕
                //                    phy_tx->send_num = 0;
                //                    phy_tx->send_state = PHY_S_INITIAL_STATE;

                //允许接收下一命令帧
                //MCU_RX_flag.cmd_valid = 0;
                //}
            }
        }else if(data[FRAME_CONTROL_CLASS] == CONTROL_CLASS_TXC){//TXC 发送卡
            if(data[FRAME_NETPORT]==0){
                Send_to_port(data,data_len,port_num,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
                Send_to_port(data,data_len,port_num,FPGA_MASTER_VBYONE2);
#endif
            }else{
                //sel_flag = ((data[FRAME_NETPORT]-1)/8);
                port_num = data[FRAME_NETPORT] - 1 ;//-8*sel_flag;//!<减一主要是程序里目前从0开始计数
#if (defined OUTPUT_BOARD_2)
                if(port_num > g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM-1){
                    sel_flag = FPGA_MASTER_VBYONE2;
                    port_num = port_num - g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM;
                }
#endif
                if(/*(port_num >= 0) && */(port_num < 0x20)){
                    addr = port_num % 4;
                    data[1] |= (addr << 4);
                    //!<因为替换的是0x00，这里直接把校验码异或一下就是新的校验码
                    data[data_len - 1] ^= (addr << 4);
                }
                //if(sel_flag>1){
                //valid=0;
                //}else{
                Send_to_port(data,data_len,port_num,sel_flag);
                //}

            }

            //if(valid){
            //透传过成
            //                phy_tx->send_flag = PHY_S_INITIAL_FLAG;	                //!<发送完毕
            //                phy_tx->send_num = 0;
            //                phy_tx->send_state = PHY_S_INITIAL_STATE;

            //允许接收下一命令帧
            //MCU_RX_flag.cmd_valid = 0;
            //}
        }
    }else{
        //valid =0;

        //if(valid){
        //透传过成
        //            phy_tx->send_flag = PHY_S_INITIAL_FLAG;	                //!<发送完毕
        //            phy_tx->send_num = 0;
        //            phy_tx->send_state = PHY_S_INITIAL_STATE;

        //允许接收下一命令帧
        //MCU_RX_flag.cmd_valid = 0;
        //}
    }

    //if(valid==0){
    //    valid=0;
    //}

    return valid ;
}

Ouint32 fpga_manage::check_netport_card(void)
{
    Ouint16 CardNum;
    Ouint8 /*ret,*/sel_fpag=0;

    if((MCU_RAM_PARA_func[sel_fpag][0x60]&0x01) == 0){
        MCU_RAM_PARA_func[sel_fpag][0x64] = 0 ;
        MCU_RAM_PARA_func[sel_fpag][0x65] = 0 ;
    }
    //网口1
    CardNum = (MCU_RAM_PARA_func[sel_fpag][0x64])|(MCU_RAM_PARA_func[sel_fpag][0x65]<<8);

    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x66])|(MCU_RAM_PARA_func[sel_fpag][0x67]<<8)) ){
        //网口2
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x66])|(MCU_RAM_PARA_func[sel_fpag][0x67]<<8));
    }

    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x6C])|(MCU_RAM_PARA_func[sel_fpag][0x6D]<<8)) ){
        //网口3
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x6C])|(MCU_RAM_PARA_func[sel_fpag][0x6D]<<8));
    }

    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x6E])|(MCU_RAM_PARA_func[sel_fpag][0x6F]<<8)) ){
        //网口4
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x6E])|(MCU_RAM_PARA_func[sel_fpag][0x6F]<<8));
    }

    //网口5
    if( CardNum>((MCU_RAM_PARA_func[sel_fpag][0x230])|(MCU_RAM_PARA_func[sel_fpag][0x231]<<8)) ){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x230])|(MCU_RAM_PARA_func[sel_fpag][0x231]<<8));
    }
    //网口6
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x234])|(MCU_RAM_PARA_func[sel_fpag][0x235]<<8)) ){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x234])|(MCU_RAM_PARA_func[sel_fpag][0x235]<<8));
    }
    //网口7
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x238])|(MCU_RAM_PARA_func[sel_fpag][0x239]<<8))){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x238])|(MCU_RAM_PARA_func[sel_fpag][0x239]<<8));
    }
    //网口8
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x23C])|(MCU_RAM_PARA_func[sel_fpag][0x23D]<<8))){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x23C])|(MCU_RAM_PARA_func[sel_fpag][0x23D]<<8));
    }

    sel_fpag=0;
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x64])|(MCU_RAM_PARA_func[sel_fpag][0x65]<<8)) ){
        //网口1
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x64])|(MCU_RAM_PARA_func[sel_fpag][0x65]<<8));
    }

    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x66])|(MCU_RAM_PARA_func[sel_fpag][0x67]<<8)) ){
        //网口2
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x66])|(MCU_RAM_PARA_func[sel_fpag][0x67]<<8));
    }

    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x6C])|(MCU_RAM_PARA_func[sel_fpag][0x6D]<<8)) ){
        //网口3
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x6C])|(MCU_RAM_PARA_func[sel_fpag][0x6D]<<8));
    }

    if(CardNum>(((MCU_RAM_PARA_func[sel_fpag][0x6E])|(MCU_RAM_PARA_func[sel_fpag][0x6F]<<8))) ){
        //网口4
        CardNum = (((MCU_RAM_PARA_func[sel_fpag][0x6E])|(MCU_RAM_PARA_func[sel_fpag][0x6F]<<8)));
    }

    //网口5
    if( CardNum>((MCU_RAM_PARA_func[sel_fpag][0x230])|(MCU_RAM_PARA_func[sel_fpag][0x231]<<8)) ){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x230])|(MCU_RAM_PARA_func[sel_fpag][0x231]<<8));
    }
    //网口6
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x234])|(MCU_RAM_PARA_func[sel_fpag][0x235]<<8)) ){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x234])|(MCU_RAM_PARA_func[sel_fpag][0x235]<<8));
    }
    //网口7
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x238])|(MCU_RAM_PARA_func[sel_fpag][0x239]<<8))){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x238])|(MCU_RAM_PARA_func[sel_fpag][0x239]<<8));
    }
    //网口8
    if(CardNum>((MCU_RAM_PARA_func[sel_fpag][0x23C])|(MCU_RAM_PARA_func[sel_fpag][0x23D]<<8))){
        CardNum = ((MCU_RAM_PARA_func[sel_fpag][0x23C])|(MCU_RAM_PARA_func[sel_fpag][0x23D]<<8));
    }

    return CardNum;
}



bool fpga_manage::wait_fpga_send_ready(Ouint8 port_num,Ouint8 sel_fpga)
{
    Ouint8 reg_addr,temp;
    Ouint32 timeout;

    if(port_num < 8){
        reg_addr = FPGA_STATE2_REG;
        temp = port_num / 2;
    }else if(port_num < 16){
        reg_addr = FPGA_STATE4_REG;
        temp = (port_num - 8) / 2;
    }else{
        return false;
    }

    timeout=G_timeTicks;

    while(Utils::getTimeSpace(timeout)<= 300){

        read_from_register(reg_addr,sel_fpga);
        if(((MCU_REG_func[sel_fpga][reg_addr] >> (temp * 2 + 1)) & 0x01) == 0){
            return true;
        }

    }


    return false;
}

void fpga_manage::rxc_lock_cmd_create(Ouint8 port_num,Ouint8* SEND_RXC_LOCK_CMD)
{
    Ouint8 i,xor_c,temp;
    Ouint8 random_num[32] = {0};
    Ouint8 old_secret[16] = {0};
    Ouint8 new_secret[16] = {0};

    //Ouint8 SEND_RXC_LOCK_CMD[76];//9+66+1
    Ouint16 data_len = 75,length;
    PhyData_Type *msg;

    msg = (PhyData_Type *)SEND_RXC_LOCK_CMD;

    //msg->DstAddr = 0x0000;
    temp = port_num % 4;
    if(temp == 1){
        msg->dstAddr = 0x0ffe;
    }else if(temp == 2){
        msg->dstAddr = 0x1ffe;
    }else if(temp == 3){
        msg->dstAddr = 0x2ffe;
    }else{
        msg->dstAddr = 0x3ffe;
    }
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x66;
    msg->controlClass = 0x01;
    msg->reserved0 = 0;
    msg->reserved1 = 0;

    msg->cmd = 0x38;
    msg->data[0] = 0x01;  //lock

    srand((unsigned)time(NULL));
    for(i = 0; i < 32; i++){
        random_num[i] = rand()%256;
        msg->data[1+i] = random_num[i];
    }

    for(i = 0; i < 16; i++){
        old_secret[i] = timeout_buf[85+i];
        msg->data[33+i] = old_secret[i] ^ random_num[i];
    }

    for(i = 0; i < 16; i++){
        new_secret[i] = timeout_buf[58+i];//i+1;
        msg->data[49+i] = new_secret[i] ^ random_num[16+i];
    }

    data_len = 76;//!<10+65+1
    length = data_len - 1;
    xor_c = Utils::BCC((Ouint8 *)SEND_RXC_LOCK_CMD,length);
    msg->data[65] = xor_c;

    return ;
}

void fpga_manage::rxc_lock_cmd_create1(Ouint8* SEND_RXC_LOCK_CMD)
{
    Ouint8 i,xor_c;
    Ouint8 random_num[32] = {0};
    Ouint8 old_secret[16] = {0};
    Ouint8 new_secret[16] = {0};


    Ouint16 data_len = 75,length;
    PhyData_Type *msg;

    msg = (PhyData_Type *)SEND_RXC_LOCK_CMD;

    msg->dstAddr = 0x0fff;
    msg->srcAdd = FPGA_DEFAULT_ADDR;//MCU_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x66;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = 0xff;
    msg->reserved1 = 0;
    msg->cmd = 0x38;
    msg->data[0] = 0x01;  //lock

    srand((unsigned)time(NULL));
    for(i = 0; i < 32; i++){
        random_num[i] = rand()%256;
        msg->data[1+i] = random_num[i];
    }

    for(i = 0; i < 16; i++){
        old_secret[i] = timeout_buf[85+i];
        msg->data[33+i] = old_secret[i] ^ random_num[i];
    }

    for(i = 0; i < 16; i++){
        new_secret[i] = timeout_buf[58+i];//i+1;
        msg->data[49+i] = new_secret[i] ^ random_num[16+i];
    }

    data_len = 76;//!<10+65+1
    length = data_len - 1;
    xor_c = Utils::BCC((Ouint8 *)SEND_RXC_LOCK_CMD,length);
    msg->data[65] = xor_c;

    return ;
}



void fpga_manage::rxc_unlock_cmd_create(Ouint8 port_num,Ouint8* SEND_RXC_LOCK_CMD)
{
    Ouint8 i,xor_c,temp;
    Ouint8 random_num[32] = {0};
    Ouint8 old_secret[16] = {0};
    Ouint8 new_secret[16] = {0};

    //Ouint8 SEND_RXC_LOCK_CMD[76];//9+66+1
    Ouint16 data_len = 75,length;
    PhyData_Type *msg;

    msg = (PhyData_Type *)SEND_RXC_LOCK_CMD;

    //msg->DstAddr = 0x0000;
    temp = port_num % 4;
    if(temp == 1){
        msg->dstAddr = 0x0ffe;
    }else if(temp == 2){
        msg->dstAddr = 0x1ffe;
    }else if(temp == 3){
        msg->dstAddr = 0x2ffe;
    }else{
        msg->dstAddr = 0x3ffe;
    }
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x66;
    msg->controlClass = 0x01;
    msg->reserved0 = 0;
    msg->reserved1 = 0;

    msg->cmd = 0x38;
    msg->data[0] = 0x00;  //unlock

    srand((unsigned)time(NULL));
    for(i = 0; i < 32; i++){
        random_num[i] = rand()%256;
        msg->data[1+i] = random_num[i];
    }

    for(i = 0; i < 16; i++){
        new_secret[i] = timeout_buf[58+i];//i+1;
        msg->data[33+i] = new_secret[i] ^ random_num[i];
    }

    for(i = 0; i < 16; i++){
        old_secret[i] = timeout_buf[85+i];//i+1;
        msg->data[49+i] = old_secret[i] ^ random_num[i];
    }

    data_len = 76;//!<10+65+1
    length = data_len - 1;
    xor_c = Utils::BCC((Ouint8 *)SEND_RXC_LOCK_CMD,length);
    msg->data[65] = xor_c;

    return ;
}

void fpga_manage::rxc_unlock_cmd_create1(Ouint8* SEND_RXC_LOCK_CMD)
{
    Ouint8 i,xor_c;
    Ouint8 random_num[32] = {0};
    Ouint8 old_secret[16] = {0};
    Ouint8 new_secret[16] = {0};

    //Ouint8 SEND_RXC_LOCK_CMD[76];//9+66+1
    Ouint16 data_len = 75,length;
    PhyData_Type *msg;

    msg = (PhyData_Type *)SEND_RXC_LOCK_CMD;

    msg->dstAddr = 0x0fff;
    msg->srcAdd = FPGA_DEFAULT_ADDR;//MCU_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x66;
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = 0xff;
    msg->reserved1 = 0;
    msg->cmd = 0x38;
    msg->data[0] = 0x00;  //unlock

    srand((unsigned)time(NULL));
    for(i = 0; i < 32; i++){
        random_num[i] = rand()%256;
        msg->data[1+i] = random_num[i];
    }

    for(i = 0; i < 16; i++){
        new_secret[i] = timeout_buf[58+i];//i+1;
        msg->data[33+i] = new_secret[i] ^ random_num[i];
    }

    for(i = 0; i < 16; i++){
        old_secret[i] = timeout_buf[85+i];//i+1;
        msg->data[49+i] = old_secret[i] ^ random_num[i];
    }

    data_len = 76;//!<10+65+1
    length = data_len - 1;
    xor_c = Utils::BCC((Ouint8 *)SEND_RXC_LOCK_CMD,length);
    msg->data[65] = xor_c;

    return ;
}



void fpga_manage::rxc_unbind_cmd_create(Ouint8 port_num,Ouint8* SEND_RXC_LOCK_CMD,Ouint8 bind)
{
    Ouint8 i,xor_c,temp;
    Ouint8 random_num[20] = {0};
    Ouint8 old_secret[16] = {0};
    Ouint8 new_secret[16] = {0};

    //Ouint8 SEND_RXC_LOCK_CMD[76];//9+66+1
    Ouint16 data_len = 75,length;
    PhyData_Type *msg;

    msg = (PhyData_Type *)SEND_RXC_LOCK_CMD;

    //msg->DstAddr = 0x0000;
    temp = port_num % 4;
    if(temp == 1){
        msg->dstAddr = 0x0ffe;
    }else if(temp == 2){
        msg->dstAddr = 0x1ffe;
    }else if(temp == 3){
        msg->dstAddr = 0x2ffe;
    }else{
        msg->dstAddr = 0x3ffe;
    }
    msg->srcAdd = FPGA_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x66;
    msg->controlClass = 0x01;
    msg->reserved0 = 0;
    msg->reserved1 = 0;

    msg->cmd = 0x39;
    msg->data[0] = bind;  //unlock

    srand((unsigned)time(NULL));
    for(i = 0; i < 20; i++){
        random_num[i] = rand()%256;
        msg->data[1+i] = random_num[i];
    }

    if(bind == 0){
        for(i = 0; i < 16; i++){
            new_secret[i] = timeout_buf[85+i];//i+1;
            msg->data[21+i] = new_secret[i] ^ random_num[i];
        }

    }else{
        for(i = 0; i < 16; i++){
            new_secret[i] = timeout_buf[58+i];//i+1;
            msg->data[21+i] = new_secret[i] ^ random_num[i];
        }
    }

    for(i = 0; i < 4; i++){
        old_secret[i] = (device_id >> (i*8)) & 0xff ;
        msg->data[37+i] = old_secret[i] ^ random_num[i+16];
    }

    data_len = 52;//!<10+65+1
    length = data_len - 1;
    xor_c = Utils::BCC((Ouint8 *)SEND_RXC_LOCK_CMD,length);
    msg->data[41] = xor_c;

    return ;
}


void fpga_manage::rxc_unbind_cmd_create1(Ouint8* SEND_RXC_LOCK_CMD,Ouint8 bind,Ouint8 sec_type)
{
    Ouint8 i,xor_c;
    Ouint8 random_num[20] = {0};
    Ouint8 old_secret[16] = {0};
    Ouint8 new_secret[16] = {0};

    //Ouint8 SEND_RXC_LOCK_CMD[76];//9+66+1
    Ouint16 data_len = 75,length;
    PhyData_Type *msg;

    msg = (PhyData_Type *)SEND_RXC_LOCK_CMD;

    msg->dstAddr = 0x0fff;
    msg->srcAdd = FPGA_DEFAULT_ADDR;//MCU_DEFAULT_ADDR;
    msg->protocolType = 0x10;
    msg->msgSeq = 0x66; //不要修改
    g_net_frame_seq = 0;//msg->msgSeq; //不要修改
    msg->controlClass = CONTROL_CLASS_RCV;
    msg->reserved0 = 0xff;//不要修改
    msg->reserved1 = 0;

    msg->cmd = 0x39;
    msg->data[0] = bind;  //unlock

    srand((unsigned)time(NULL));
    for(i = 0; i < 20; i++){
        random_num[i] = rand()%256;
        msg->data[1+i] = random_num[i];
    }

    /*if(bind == 0){
        for(i = 0; i < 16; i++){
           new_secret[i] = timeout_buf[85+i];//i+1;
            msg->data[21+i] = new_secret[i] ^ random_num[i];
        }

    }else*/{
        for(i = 0; i < 16; i++){
            if(sec_type == 0x00){
                new_secret[i] = timeout_buf[58+i];//i+1;
            }else{
                new_secret[i] = timeout_buf[85+i];//i+1;
            }
            msg->data[21+i] = new_secret[i] ^ random_num[i];
        }
    }

    for(i = 0; i < 4; i++){
        old_secret[i] = (device_id >> (i*8)) & 0xff ;
        msg->data[37+i] = old_secret[i] ^ random_num[i+16];
    }

    data_len = 52;//!<10+65+1
    length = data_len - 1;
    xor_c = Utils::BCC((Ouint8 *)SEND_RXC_LOCK_CMD,length);
    msg->data[41] = xor_c;

    return ;
}


Ouint8 fpga_manage::to_rcv_sure_send(Ouint8 status ,Ouint32 len, Ouint8 *data)
{
    Ouint32 ret,turn = 0;
    Ouint16 wlan_state[2];
    Ouint8 addr;
    Ouint8 status1;

    Ouint8 i;

    //判断是否允许发送搜索帧


    status1 = status;


    if(status1 == TO_RCV_BIND_STATUS_START){
        //delay
        g_timeout_ticks = G_timeTicks;
        return TO_RCV_BIND_RESULT_NEXT;


    }else if(status1 == TO_RCV_BIND_STATUS_WAIT){
        if(Utils::getTimeSpace(g_timeout_ticks) > SEARCH_ORDER_DELAY){
            g_timeout_ticks = G_timeTicks;
            g_netport_to_rcv_sure_recored = 0;
            to_rcv_sure_error = 0;
            //g_fpga_ack_statue = 0;
            to_rcv_sure_cmd_39 = 0;

            return TO_RCV_BIND_RESULT_NEXT;
        }
        return TO_RCV_BIND_RESULT_WAIT;
    }else if(status1 == TO_RCV_BIND_STATUS_SEND_HALF1 || status1 == TO_RCV_BIND_STATUS_SEND_HALF2){
        to_rcv_sure_checktimes = 0;

        if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03){
            wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
        }else{
            wlan_state[0] = 0x00;
        }
#if (defined OUTPUT_BOARD_2)
        if(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] == 0x03){
            wlan_state[1] = (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];
        }else{
            wlan_state[1] = 0x00;
        }
#endif

        if(status1 == TO_RCV_BIND_STATUS_SEND_HALF1){
            turn = 0;
        }else{
            turn = 1;

        }

        //每800ms读取一次
        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE1);//读取FPGA状态寄存器
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE1);//读取FPGA状态寄存器

#if (defined OUTPUT_BOARD_2)
        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE2);//读取FPGA状态寄存器
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE2);//读取FPGA状态寄存器
#endif

        if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03){
            wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
        }else{
            wlan_state[0] = 0x00;
        }
#if (defined OUTPUT_BOARD_2)
        if(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] == 0x03){
            wlan_state[1] = (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];
        }else{
            wlan_state[1] = 0x00;
        }
#endif


        if(turn == 0){//!<同连接下，优先0、2、4、6
            for(ret=0;ret<(g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM/2);ret++){
                for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){
                    if(((((wlan_state[i]>>(2*ret))&0x01)== 1)&&(get_port_card_num(i*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + 2*ret)!=0))){

                        //if( (g_netport_to_rcv_sure_recored >> (i*OUT_PORT_NUM + 2*ret)) & 0x01 ){
                        //     break;
                        //}
                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);

                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif


                        data[len - 1] ^= data[1];//去掉该位异或值
                        data[1] &= 0xcf;//!<端口号清零

                        addr = (2*ret) % 4; // 0  2  0 2 0 2 0 2
                        data[1] |= (addr << 4);

                        data[len - 1] ^= data[1];

                        Send_to_port(data,len,2*ret,i);

                        g_netport_to_rcv_sure_recored |=  (1 << (i*OUT_PORT_NUM + 2*ret));


                    }else if( ((((wlan_state[i]>>(2*ret+1))&0x01) == 1)&&(get_port_card_num(i*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + 2*ret+1)!=0))){

                        //if( (g_netport_to_rcv_sure_recored >> (i*OUT_PORT_NUM + 2*ret + 1)) & 0x01 ){
                        //    break;
                        //}


                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);
                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif

                        data[len - 1] ^= data[1];//去掉该位异或值
                        data[1] &= 0xcf;//!<端口号清零

                        addr = (2*ret+1) % 4;// 1  3  1 3 1 3 1 3
                        data[1] |= (addr << 4);

                        data[len - 1] ^= data[1];

                        Send_to_port(data,len,2*ret+1,i);
                        g_netport_to_rcv_sure_recored |=  (1 << (i*OUT_PORT_NUM + 2*ret +1));

                    }
                }
            }

        }else{

            for(ret=0;ret<(g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM/2);ret++){
                for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){
                    if( ((((wlan_state[i]>>(2*ret+1))&0x01) == 1)&&(get_port_card_num(i*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + 2*ret+1)!=0))){

                        //if( (g_netport_to_rcv_sure_recored >> (i*OUT_PORT_NUM + 2*ret + 1)) & 0x01 ){
                        //    break;
                        //}


                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);
                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif

                        data[len - 1] ^= data[1];//去掉该位异或值
                        data[1] &= 0xcf;//!<端口号清零

                        addr = (2*ret+1) % 4;// 1  3  1 3 1 3 1 3
                        data[1] |= (addr << 4);

                        data[len - 1] ^= data[1];

                        Send_to_port(data,len,2*ret+1,i);
                        g_netport_to_rcv_sure_recored |=  (1 << (i*OUT_PORT_NUM + 2*ret +1));

                    }else  if(((((wlan_state[i]>>(2*ret))&0x01)== 1)&&(get_port_card_num(i*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + 2*ret)!=0))){

                        // if( (g_netport_to_rcv_sure_recored >> (i*OUT_PORT_NUM + 2*ret)) & 0x01 ){
                        //    break;
                        // }
                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);

                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif


                        data[len - 1] ^= data[1];//去掉该位异或值
                        data[1] &= 0xcf;//!<端口号清零

                        addr = (2*ret) % 4; // 0  2  0 2 0 2 0 2
                        data[1] |= (addr << 4);

                        data[len - 1] ^= data[1];

                        Send_to_port(data,len,2*ret,i);

                        g_netport_to_rcv_sure_recored |=  (1 << (i*OUT_PORT_NUM + 2*ret));

                    }
                }
            }
        }

        g_timeout_ticks = G_timeTicks;
        return TO_RCV_BIND_RESULT_NEXT;

    }else if(status1 == TO_RCV_BIND_STATUS_WAITHFALF1_RESUT || status1 == TO_RCV_BIND_STATUS_WAITHFALF2_RESUT){

        if(Utils::getTimeSpace(g_timeout_ticks) > 10){//100ms
            Ouint8 check_00 = 0;
            for(ret=0;ret<OUT_PORT_NUM;ret++){
                for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){
                    if( g_netport_to_rcv_sure_recored >> (ret + i* OUT_PORT_NUM) ){
                        if(/*g_fpga_ack_statue*/to_rcv_sure_cmd_39 >> (ret + i* OUT_PORT_NUM )) {
                            continue;
                        }else{
                            check_00 = 1;
                        }
                    }
                }
            }


            //to_rcv_sure_checktimes = 0;
            g_timeout_ticks = G_timeTicks;
            if(check_00 == 0){

                to_rcv_sure_error = 0 ;
                //next
                if(status1 == TO_RCV_BIND_STATUS_WAITHFALF1_RESUT){
                    BX_printf("\n half all have ack , %d ,%#x ,%#x,%#x\n",to_rcv_sure_checktimes ,g_fpga_ack_statue,g_netport_to_rcv_sure_recored,to_rcv_sure_cmd_39);
                    return TO_RCV_BIND_RESULT_NEXT;
                }else if(status1 == TO_RCV_BIND_STATUS_WAITHFALF2_RESUT){
                    BX_printf("\n all all have ack %d ,%#x ,%#x,%#x\n",to_rcv_sure_checktimes ,g_fpga_ack_statue,g_netport_to_rcv_sure_recored,to_rcv_sure_cmd_39);
                    return TO_RCV_BIND_RESULT_OVER;
                }


            }else{

                to_rcv_sure_checktimes++;
                if(to_rcv_sure_checktimes >= 10*3){//3s

                    to_rcv_sure_checktimes = 0;
                    to_rcv_sure_error++;
                    g_netport_to_rcv_sure_recored &= (~(1 << (ret + i* OUT_PORT_NUM))) ;
                }


                if(to_rcv_sure_error ){
                    if( to_rcv_sure_error < 3){
                        //retry
                        BX_printf("\n  try again ....\n");
                        return TO_RCV_BIND_RESULT_BACK;

                    }else{
                        to_rcv_sure_error = 0 ;
                        //next
                        BX_printf("\n  sending failed ....\n");
                        if(status1 == TO_RCV_BIND_STATUS_WAITHFALF1_RESUT){
                            return TO_RCV_BIND_RESULT_NEXT;
                        }else if(status1 == TO_RCV_BIND_STATUS_WAITHFALF2_RESUT){
                            return TO_RCV_BIND_RESULT_OVER;
                        }

                    }
                }else{

                    //wait statuw
                    BX_printf("\n  waiting ....to_rcv_sure_checktimes = %d ,%#x ,%#x,%#x\n",to_rcv_sure_checktimes ,g_fpga_ack_statue,g_netport_to_rcv_sure_recored,to_rcv_sure_cmd_39);
                    return TO_RCV_BIND_RESULT_WAIT;
                }
            }
        }
    }
    return -1;
}



void fpga_manage::send_rxc_lock_cmd(void)
{
    Ouint8 SEND_RXC_LOCK_CMD[76];
    Ouint16 data_len,length,i,j=0;

    data_len = 76;//!<9+66+1
    length = data_len - 1;


    for(j = 0; j < g_Global->OVP_CONTROL_OUT_NUM ; j++){
        for(i = 0; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM ; i++){

            if(wait_fpga_send_ready(i,j) == true){
                rxc_lock_cmd_create(i,SEND_RXC_LOCK_CMD);
                Send_to_port(SEND_RXC_LOCK_CMD,sizeof(SEND_RXC_LOCK_CMD),i,j);
            }

        }
    }
    return ;
}

void fpga_manage::send_rxc_unlock_cmd(void)
{
    Ouint8 SEND_RXC_UNLOCK_CMD[76];
    Ouint16 data_len,length,i,j=0;

    // data_len = 76;//!<9+66+1
    //length = data_len - 1;


    for(j = 0; j < g_Global->OVP_CONTROL_OUT_NUM ; j++){
        for(i = 0; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM ; i++){

            if(wait_fpga_send_ready(i,j) == true){
                rxc_unlock_cmd_create(i,SEND_RXC_UNLOCK_CMD);
                Send_to_port(SEND_RXC_UNLOCK_CMD,sizeof(SEND_RXC_UNLOCK_CMD),i,j);
            }

        }
    }
    return ;
}


Ouint8 fpga_manage::send_device_rcv_bind_cmd(Ouint8 bind, Ouint8 status, Ouint8 sec_type)
{
    Ouint8 SEND_RXC_UNLOCK_CMD[52];
    Ouint8 ret = 0,ret1;
    /*uint16 data_len,length,i,j=0;

    data_len = 76;//!<9+66+1
    length = data_len - 1;


    for(j = 0; j < g_Global->OVP_CONTROL_OUT_NUM ; j++){
        for(i = 0; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM ; i++){

            if(wait_fpga_send_ready(i,j) == true){
                  rxc_unbind_cmd_create(i,SEND_RXC_UNLOCK_CMD,bind);
                  Send_to_port(SEND_RXC_UNLOCK_CMD,sizeof(SEND_RXC_UNLOCK_CMD),i,j);
            }

        }
    }*/

    rxc_unbind_cmd_create1(SEND_RXC_UNLOCK_CMD,bind,sec_type);

    ret1 = to_rcv_sure_send(to_rcv_sure_status,52,SEND_RXC_UNLOCK_CMD);

    if(ret1 == TO_RCV_BIND_RESULT_NEXT){
        to_rcv_sure_status++;
    }else if(ret1 == TO_RCV_BIND_RESULT_BACK){
        to_rcv_sure_status--;

    }else if(ret1 == TO_RCV_BIND_RESULT_OVER){

        to_rcv_sure_status = 2;
        ret = 1;
    }
    return ret;
}



void fpga_manage::rxc_lock_set(void)
{
    Ouint8 status ;
    //if(g_fpga_change.fun_timeout_lock == 0){
#if 0
    if((Timeout_flag & 0x02) == 0){
        return;
    }

    if(Utils::getTimeSpace(g_timeout_ticks) > TIMEOUT_DELAY){

        send_rxc_lock_cmd();

        g_timeout_ticks = G_timeTicks;
    }
#endif


    if(/*g_fpga_change.fun_timeout_enable == FUNCTION_ENABLE*/Timeout_flag & 0x01){
        if(/*g_fpga_change.fun_timeout_lock == 1*/Timeout_flag & 0x02){

            if((Utils::getTimeSpace(g_timeout_ticks) > TIMEOUT_DELAY) || (rcv_locksend_over == OVP_RCV_LOCK_ACT_ZERO)|| (rcv_locksend_over >= OVP_RCV_LOCK_ACT_ATONCE)){
                if(new_check_time == true){
                    return;
                }
                if(rcv_locksend_over == /*2*/OVP_RCV_LOCK_CHANGE_PASSWORD){ //change password
                    if(to_rcv_sure_cmd_num == 0){
                        status = send_device_rcv_bind_cmd(0x00,to_rcv_sure_status,0x01); //0x00 new screate
                        if(status == 0){
                            return ;
                        }
                        to_rcv_sure_cmd_num++;
                        sleep(1);
                        return;
                    }else{
                        status = send_device_rcv_bind_cmd(0x01,to_rcv_sure_status,0x00);
                        if(status == 0){
                            return ;
                        }
                        sleep(1);
                        to_rcv_sure_cmd_num=0;
                    }
                }
                send_rxc_lock_cmd();
                g_timeout_ticks = G_timeTicks;
                Utils::_rcv_lockor_mutex.lock();
                rcv_locksend_over = OVP_RCV_LOCK_ACT_CANCLE;
                rcv_unlocksend_over = OVP_RCV_LOCK_ACT_ZERO;
                Utils::_rcv_lockor_mutex.unlock();
            }

        }else{//对应延长试用

            if((Utils::getTimeSpace(g_timeout_ticks) > TIMEOUT_DELAY) || (rcv_unlocksend_over == OVP_RCV_LOCK_ACT_ZERO) || (rcv_unlocksend_over >= OVP_RCV_LOCK_ACT_ATONCE)){
                if(new_check_time == true){
                    return;
                }
                if(rcv_unlocksend_over == /*2*/OVP_RCV_LOCK_CHANGE_PASSWORD){//change password
                    if(to_rcv_sure_cmd_num == 0){
                        status = send_device_rcv_bind_cmd(0x00,to_rcv_sure_status,0x01); //0x00 new screate
                        if(status == 0){
                            return ;
                        }
                        sleep(1);

                        to_rcv_sure_cmd_num++;
                        sleep(1);
                        return;

                    }else{
                        status = send_device_rcv_bind_cmd(0x01,to_rcv_sure_status,0x00);
                        if(status == 0){
                            return ;
                        }
                        sleep(1);
                    }
                }
                send_rxc_unlock_cmd();
                g_timeout_ticks = G_timeTicks;
                Utils::_rcv_lockor_mutex.lock();
                rcv_locksend_over = OVP_RCV_LOCK_ACT_ZERO;
                rcv_unlocksend_over = OVP_RCV_LOCK_ACT_CANCLE;
                Utils::_rcv_lockor_mutex.unlock();
            }

        }
    }else{//对应转正
        if(timeout_buf[84] == 0x01){//已经转正
            if((Utils::getTimeSpace(g_timeout_ticks) > TIMEOUT_DELAY)|| (rcv_unlocksend_over == OVP_RCV_LOCK_ACT_ZERO) || (rcv_unlocksend_over >= OVP_RCV_LOCK_ACT_ATONCE)){
                if(new_check_time == true){
                    return;
                }
                if(rcv_unlocksend_over == /*2*/OVP_RCV_LOCK_IMMEDIATE_PROBATION){
                    status = send_device_rcv_bind_cmd(0x00,to_rcv_sure_status,0x00); //0x00 new screate
                    if(status == 0){
                        return ;
                    }
                    sleep(1);
                }
                send_rxc_unlock_cmd();
                g_timeout_ticks = G_timeTicks;
                Utils::_rcv_lockor_mutex.lock();
                rcv_locksend_over = OVP_RCV_LOCK_ACT_ZERO;
                rcv_unlocksend_over = OVP_RCV_LOCK_ACT_CANCLE;
                Utils::_rcv_lockor_mutex.unlock();
            }
        }
    }

}

void fpga_manage::multi_port_send(Ouint8* data, Ouint16 data_len)
{
    //Ouint8 data2,data1;
    Ouint16 /*port_num,*/ret,i,addr;
    //PHY_TX* phy_tx;
    //uint32 timeout,net_valid=0;

    Ouint16 wlan_state[2];

    // data_len = phy_tx->send_len;
    //先将数据取出
    //上排
    /*for(ret=0;ret<DEVICE_OUT_NUM/2;ret++){
        for(i=0;i<2;i++){
            net_wati_send_flag[i][ret]=0;
        }
    }*/
    bool fpga_multicast_mode = false;

    Utils::_fpga_multicast_mutex.lock();
    fpga_multicast_mode = set_fpga_multicast_mode;

    wlan_state[0] = fpga_multicast_net & 0xFF;
    wlan_state[1] = 0x00;
#if (defined OUTPUT_BOARD_2)
    wlan_state[1] = (fpga_multicast_net >> 16) & 0xFF;
#endif

    Utils::_fpga_multicast_mutex.unlock();

    if(fpga_multicast_mode == false){
        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE1);//FPGA状态寄存器[接收数据是否有效]
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE1);//FPGA状态寄存器[接收数据是否有效]
#if (defined OUTPUT_BOARD_2)
        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE2);//FPGA状态寄存器[接收数据是否有效]
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE2);//FPGA状态寄存器[接收数据是否有效]
#endif
        //    read_from_register(FPGA_STATE2_REG,FPGA_SLAVER_NEAR_OUTMINTOR);//FPGA状态寄存器[接收数据是否有效]

        //wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
        //wlan_state[1] = 0x00;//(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];


        if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03){
            wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
        }else{
            wlan_state[0] = 0x00;
        }
#if (defined OUTPUT_BOARD_2)
        if(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] == 0x03){
            wlan_state[1] = (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];
        }else{
            wlan_state[1] = 0x00;
        }
#endif


        for(ret=0;ret<(g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM/2);ret++){
            for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){

                if(((((wlan_state[i]>>(2*ret))&0x01)== 1)&&(get_port_card_num(i*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + 2*ret)!=0))){

                    //直接发送网口
                    data[data_len - 1] ^= data[1];//去掉该位异或值
                    data[1] &= 0xcf;//!<端口号清零

                    addr = (2*ret) % 4; // 0  2  0 2 0 2 0 2
                    data[1] |= (addr << 4);

                    data[data_len - 1] ^= data[1];

                    //if(wait_fpga_send_ready(2*ret,i) == true){
                    Send_to_port(data,data_len,2*ret,i);//0,2,4,6,8,10,12,14
                    //BX_printf("\n multi_port_send(%#x,%#x) \n",2*ret,i) ;
                    //}else{
                    //BX_printf("\n fpga%d port%d busy!! \n",i,2*ret+1);
                    //}
                    //net_wati_send_flag[i][ret] = ((wlan_state[i]>>(2*ret+1))&0x01) ;

                }/*else *by chenyd change test **/if( ((((wlan_state[i]>>(2*ret+1))&0x01) == 1)&&(get_port_card_num(i*g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + 2*ret+1)!=0))){

                    //直接发送网口
                    data[data_len - 1] ^= data[1];//去掉该位异或值
                    data[1] &= 0xcf;//!<端口号清零

                    addr = (2*ret+1) % 4;// 1  3  1 3 1 3 1 3
                    data[1] |= (addr << 4);

                    data[data_len - 1] ^= data[1];

                    //if(wait_fpga_send_ready(2*ret,i) == true){
                    Send_to_port(data,data_len,2*ret+1,i);//1,3,5,7,9,11,13,15
                    //BX_printf("\n multi_port_send(%#x,%#x) \n",2*ret+1,i) ;
                    //}else{
                    //BX_printf("\n fpga%d port%d busy!! \n",i,2*ret+2);
                    //}

                }


            }
        }
    }else{
        for(ret=0;ret<(g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM/2);ret++){
            for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){

                if(((wlan_state[i]>>(2*ret))&0x01) == 1){

                    //直接发送网口
                    data[data_len - 1] ^= data[1];//去掉该位异或值
                    data[1] &= 0xcf;//!<端口号清零

                    addr = (2*ret) % 4; // 0  2  0 2 0 2 0 2
                    data[1] |= (addr << 4);
                    data[data_len - 1] ^= data[1];
                    Send_to_port(data,data_len,2*ret,i);//0,2,4,6,8,10,12,14

                }/*else *by chenyd change test **/if( ((wlan_state[i]>>(2*ret+1))&0x01) == 1){
                    //直接发送网口
                    data[data_len - 1] ^= data[1];//去掉该位异或值
                    data[1] &= 0xcf;//!<端口号清零

                    addr = (2*ret+1) % 4;// 1  3  1 3 1 3 1 3
                    data[1] |= (addr << 4);

                    data[data_len - 1] ^= data[1];
                    Send_to_port(data,data_len,2*ret+1,i);//1,3,5,7,9,11,13,15

                }
            }
        }
    }


    g_check_netport_trans_mode = 1;
    //g_sync_netport_trans_setup = 0;
    g_netport_trans_ticks = G_timeTicks;
    //BX_printf("\n multi_port_send (%d)\n",G_timeTicks) ;

}


void fpga_manage::softinit(){

    // PHY_init();
    //sendCardFuncInit();
    //PCB_version_check();
    ////全局变量初始化
    g_change.sys_data_in_line = 0x0F;
    g_change.sys_data_out_line = 0x0F;
    //全局控制变量初始化
    //g_change.sys_wtd_flag = 0;
    //g_change.sys_wtd_time = 0;

    //g_change.sys_led_run_err = 0;
    //g_change.sys_VSE_master_flag=1;                 //!<主机模式
    //g_change.sys_signal_check_time = 0;
    g_change.sys_fpga_ret_time[0] = G_timeTicks;
    g_change.sys_fpga_ret_time[1] = G_timeTicks;
    //g_change.sys_start_delay_time = G_timeTicks;
    g_change.sys_fpga_delay_time[0] = G_timeTicks;
    g_change.sys_fpga_delay_time[1] = G_timeTicks;
    //g_change.sys_resolution_check_time = G_timeTicks;

    g_change.sys_check_vbo_status_ticks[0] = G_timeTicks;
    g_change.sys_check_vbo_status_ticks[1] = G_timeTicks;

    //g_change.sys_fpga_communite_enable[0]=0;
    //g_change.sys_fpga_communite_enable[1]=0;

    g_change.sys_fpga_check_net_flag[0] = 0;
    g_change.sys_fpga_check_net_flag[1] = 0;

    g_change.sys_power_init = 0;
    g_change.sys_fpga_check_init_ticks = G_timeTicks;

    Power_ctrl_init();
    //表示网口输出时
    //#ifdef OUTPUT_LEDNET
    //此时仅针对 网口输出 比如 M1X/L1X 不针对 DVI输出
    Version_to_RAM();
    //更新PHY0状态值
    PHY_status_to_RAM();
    //当前亮度等级
    MCU_RAM_CMD[0x1C] = 0xFF;
    //开关屏状态
    MCU_RAM_CMD[0x1D] = 1;
    //表示MCU支持多网口并发功能
    MCU_RAM_EXTEND[0x31] = 0x9f;//0x21;
    MCU_RAM_EXTEND[0x32] = 0x0f;
    //    g_phy_deal.phy_rx[PC_FPGA_SPI].rcv_flag = PHY_GF_INVALID;
    //#endif

    g_send_para.type = SMART_PARA_INIT;
    g_send_para.rcv_back = 0;
    g_send_para.state = 0xff;
}

void fpga_manage::Version_to_RAM(void)
{
    MCU_RAM_CMD[0x1B] = 0x00;
    MCU_RAM_CMD[0x1A] = 0x00;
    //MCU_RAM1_EXTEND[0x19] = (MCU_VER >> 8) & 0x0FF;
    //MCU_RAM1_EXTEND[0x18] = MCU_VER & 0x0FF;   APP_H1_VER0
    //这里可能要进行修改 需要调整 MCU版本
    MCU_RAM_CMD[0x19] = (0x1101 >> 8) & 0x0FF;
    MCU_RAM_CMD[0x18] = 0x1101 & 0x0FF;
}


void fpga_manage::PHY_status_to_RAM(void)
{
    Ouint16 PHY_buf[2]={0,0};
    //MII_Read_nbyte(0x00,0x01,&PHY_buf[0],1);
    //MII_Read_nbyte(0x01,0x01,&PHY_buf[1],1);
    //PHY0 PHY1芯片内的状态寄存器
    MCU_RAM_CMD[0x1E] = PHY_buf[0] & 0x0FF;
    MCU_RAM_CMD[0x1F] = (PHY_buf[0] >> 8) & 0x0FF;
    MCU_RAM_CMD[0x20] = PHY_buf[1] & 0x0FF;
    MCU_RAM_CMD[0x21] = (PHY_buf[1] >> 8) & 0x0FF;
}






//#ifdef CONCURRENT_ENABLE


void fpga_manage::update_eth_rcv_num(PhyData_Type *msg,Ouint8 port,Ouint8 sel_fpag)
{
    Ouint16 rcard_addr,fcard_addr;

    //BX_printf("\n update_eth_rcv_num card_num = %d ,port = %d , sel = %d\n",msg->data[1] , port, sel_fpag);
    switch(port){
    case 0:
        rcard_addr = ETH0_RCVL;
        fcard_addr = ETH0_VMF;
        break;
    case 1:
        rcard_addr = ETH1_RCVL;
        fcard_addr = ETH1_VMF;
        break;
    case 2:
        rcard_addr = ETH2_RCVL;
        fcard_addr = ETH2_VMF;
        break;
    case 3:
        rcard_addr = ETH3_RCVL;
        fcard_addr = ETH3_VMF;
        break;
    case 4:
        rcard_addr = ETH4_RCVL;
        fcard_addr = ETH4_VMF;
        break;
    case 5:
        rcard_addr = ETH5_RCVL;
        fcard_addr = ETH5_VMF;
        break;
    case 6:
        rcard_addr = ETH6_RCVL;
        fcard_addr = ETH6_VMF;
        break;
    case 7:
        rcard_addr = ETH7_RCVL;
        fcard_addr = ETH7_VMF;
        break;
    case 8:
        rcard_addr = ETH8_RCVL;
        fcard_addr = ETH8_VMF;
        break;
    case 9:
        rcard_addr = ETH9_RCVL;
        fcard_addr = ETH9_VMF;
        break;
    case 10:
        rcard_addr = ETH10_RCVL;
        fcard_addr = ETH10_VMF;
        break;
    case 11:
        rcard_addr = ETH11_RCVL;
        fcard_addr = ETH11_VMF;
        break;
    case 12:
        rcard_addr = ETH12_RCVL;
        fcard_addr = ETH12_VMF;
        break;
    case 13:
        rcard_addr = ETH13_RCVL;
        fcard_addr = ETH13_VMF;
        break;
    case 14:
        rcard_addr = ETH14_RCVL;
        fcard_addr = ETH14_VMF;
        break;
    case 15:
        rcard_addr = ETH15_RCVL;
        fcard_addr = ETH15_VMF;
        break;
    default:return;
    }
    //暂时先这样
    MCU_RAM_PARA_func[sel_fpag][rcard_addr] = msg->data[1];
    MCU_RAM_PARA_func[sel_fpag][rcard_addr+1] = msg->data[2];
    MCU_RAM_PARA_func[sel_fpag][fcard_addr] = msg->data[3];

    write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][rcard_addr],rcard_addr,fcard_addr-rcard_addr+1,PARA_RAM,sel_fpag);
    //read_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][rcard_addr],rcard_addr,fcard_addr-rcard_addr+1,PARA_RAM,sel_fpag);
}



/*!
*  @brief	deal_with_search_concurrent 针对搜索帧并发处理进行命令
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Search_concurrent_back_result(PhyData_Type *msg,Ouint8 group,Ouint8 sel_fpag,Ouint32 len)
{
    //PHY_RX *phy_rx;
    //PHY_HEAD *msg;
    Ouint16 rcard_addr,fcard_addr;
    Ouint32 screen_id;

    //phy_rx = &g_phy_deal.phy_rx[PC_FPGA_SPI];
    //msg = (PHY_HEAD *)phy_rx->data;

    if(msg->reserved0 == 0x00){
        msg->reserved0 = ((msg->srcAdd & 0x3000) >> (4+8)) + group * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
        //!<接收卡返回默认为0，需要手动替换
    }


//    BX_printf("\n back_port_num : %d \n",msg->reserved0 + sel_fpag * 16);

    switch(msg->reserved0 - 1){
        case 0:
        rcard_addr = ETH0_RCVL;
        fcard_addr = ETH0_VMF;
        break;
        case 1:
        rcard_addr = ETH1_RCVL;
        fcard_addr = ETH1_VMF;
        break;
        case 2:
        rcard_addr = ETH2_RCVL;
        fcard_addr = ETH2_VMF;
        break;
        case 3:
        rcard_addr = ETH3_RCVL;
        fcard_addr = ETH3_VMF;
        break;
        case 4:
        rcard_addr = ETH4_RCVL;
        fcard_addr = ETH4_VMF;
        break;
        case 5:
        rcard_addr = ETH5_RCVL;
        fcard_addr = ETH5_VMF;
        break;
        case 6:
        rcard_addr = ETH6_RCVL;
        fcard_addr = ETH6_VMF;
        break;
        case 7:
        rcard_addr = ETH7_RCVL;
        fcard_addr = ETH7_VMF;
        break;
        case 8:
        rcard_addr = ETH8_RCVL;
        fcard_addr = ETH8_VMF;
        break;
        case 9:
        rcard_addr = ETH9_RCVL;
        fcard_addr = ETH9_VMF;
        break;
        case 10:
        rcard_addr = ETH10_RCVL;
        fcard_addr = ETH10_VMF;
        break;
        case 11:
        rcard_addr = ETH11_RCVL;
        fcard_addr = ETH11_VMF;
        break;
        case 12:
        rcard_addr = ETH12_RCVL;
        fcard_addr = ETH12_VMF;
        break;
        case 13:
        rcard_addr = ETH13_RCVL;
        fcard_addr = ETH13_VMF;
        break;
        case 14:
        rcard_addr = ETH14_RCVL;
        fcard_addr = ETH14_VMF;
        break;
        case 15:
        rcard_addr = ETH15_RCVL;
        fcard_addr = ETH15_VMF;
        break;
        default:return;
    }
    //暂时先这样
    MCU_RAM_PARA_func[sel_fpag][rcard_addr] = msg->data[1];
    MCU_RAM_PARA_func[sel_fpag][rcard_addr+1] = msg->data[2];
    MCU_RAM_PARA_func[sel_fpag][fcard_addr] = msg->data[3];

    if((len >= 18)){

        screen_id = ((Ouint32)msg->data[8]) |((Ouint32)(msg->data[9] << 8)) |((Ouint32)(msg->data[10] << 16))  |((Ouint32)(msg->data[11] << 24))  ;

         //BX_printf("\n Get screen_id = %#x , config_file_id = %#x \n ", screen_id,p_rcvRecovery->rcv_screen_id_info.screen_config_id);
         //if(screen_id == p_rcvRecovery->rcv_screen_id_info.screen_config_id){
             g_send_para.rcv_back_info = msg->data[12];
        //}
    }

    /*BX_printf("\nGet len = 0x%02x\n",len);
    for(int t=0;t<len;t++){
        BX_printf(" 0x%02x ",((Ouint8 *)msg)[t]);
    }
    BX_printf("\n");*/

    //BX_printf("\n rcard1:%d rcard2:%d fcard:%d \n",MCU_RAM_PARA_func[sel_fpag][rcard_addr],MCU_RAM_PARA_func[sel_fpag][rcard_addr+1],MCU_RAM_PARA_func[sel_fpag][fcard_addr]);

    //同步到发送卡的RAM中，可以不用
    write_fpga_ram(&MCU_RAM_PARA_func[sel_fpag][rcard_addr],rcard_addr,fcard_addr-rcard_addr+1,PARA_RAM,sel_fpag);
}



/*!
*  @brief	deal_with_search_concurrent 针对搜索帧并发处理进行命令
*  @param	none
*  @return	none
*  @note	none
*/
Ouint8 fpga_manage::deal_with_search_concurrent(Ouint8 sel_fpag)
{
    PhyData_Type *msg;
    Ouint8 phy_rx[RAM_MAX_LEN];
    Ouint8 crc_xor,rcv_xor,port_num;
    Ouint8 ret = 0;
    Ouint32 eth_data_len = 0;

    read_from_register(FPGA_STATE2_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
    read_from_register(RX_RAM_HIGH_REG,sel_fpag);//接收数据有效高字节
    read_from_register(FPGA_STATE4_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
    read_from_register(RX_RAM_HIGH_REG2,sel_fpag);//接收数据有效高字节

    //phy_rx = &g_phy_deal.phy_rx[PC_FPGA_SPI];

    //网口1-2  RV状态
    if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x01){
        //read_from_register(RX_RAM_HIGH_REG,sel_fpag);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_12,sel_fpag);
        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_12] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0x03) << 8)) + 1;
        //回来的数据没有计入校验位，这里要加一，下同
        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
            //write_to_register(FPGA_CONTROL1_REG,0x01,0x01,sel_fpag);//!<使能发送
            read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_12,sel_fpag); //读取数据到MCU命令缓存中

            //!<计算除最后一位校验位以外的XOR值
            crc_xor = Utils::BCC(phy_rx, eth_data_len - 1);
            //!<接收的XOR校验值
            rcv_xor = phy_rx[eth_data_len - 1];
            msg = (PhyData_Type *)phy_rx;
            //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
            //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
            if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP/* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                if(rcv_xor == crc_xor){

                    if(msg->cmd == CMD_SEARCH_GROUP){
                        g_netport_recored1|=(1<<(0+sel_fpag*8));
                        if(msg->data[0] == 0x00){
                            Search_concurrent_back_result(msg,0,sel_fpag,eth_data_len);
                        }
                    }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                        to_rcv_sure_cmd_39 |=(1<<(0+sel_fpag*8));
                    }

                    //write_to_register(FPGA_CLEAR1_REG,0x01,0x01,sel_fpag);             //更新寄存器,数据已读取

                    //清除掉0x83
                    //write_to_register(FPGA_CONTROL1_REG,0x01,0x00,sel_fpag);//!<使能发送

                    ret=1;
                    read_from_register(FPGA_STATE2_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                }
                write_to_register(FPGA_CLEAR1_REG,0x01,0x01,sel_fpag);             //更新寄存器,数据已读取
                //清除掉0x83
                write_to_register(FPGA_CONTROL1_REG,0x01,0x00,sel_fpag);//!<使能发送
            }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 0 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                //BX_printf("\n 1/2 port_num : %d addr: %#x\n",port_num,msg->srcAdd);
                if(g_net_frame_seq==msg->msgSeq){
                    //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                }

            }
        }
    }

    if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x04){
        //read_from_register(RX_RAM_HIGH_REG,sel_fpag);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_34,sel_fpag);
        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_34] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0x0c) << 6)) + 1;
        //回来的数据没有计入校验位，这里要加一，下同
        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
            //write_to_register(FPGA_CONTROL1_REG,0x02,0x02,sel_fpag);//!<使能发送
            read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_34,sel_fpag);//读取数据到MCU命令缓存中
            //phy_rx->rcv_len = eth_data_len;
            //!<计算除最后一位校验位以外的XOR值
            crc_xor = Utils::BCC(phy_rx, eth_data_len - 1);
            //!<接收的XOR校验值
            rcv_xor = phy_rx[eth_data_len - 1];
            msg = (PhyData_Type *)phy_rx;
            //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
            //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
            if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                if(rcv_xor == crc_xor){
                    if(msg->cmd == CMD_SEARCH_GROUP){
                        g_netport_recored1|=(1<<(1+sel_fpag*8));
                        if((msg->data[0] == 0x00)){
                            Search_concurrent_back_result(msg,0,sel_fpag,eth_data_len);
                        }
                    }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                        to_rcv_sure_cmd_39 |=(1<<(1+sel_fpag*8));
                    }
                    //write_to_register(FPGA_CLEAR1_REG,0x02,0x02,sel_fpag);                  //更新寄存器,数据已读取

                    //清除掉0x83
                    //write_to_register(FPGA_CONTROL1_REG,0x02,0x00,sel_fpag);                //!<使能发送
                    ret=1;
                    read_from_register(FPGA_STATE2_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                }
                //BX_printf("\n deal_with_search_concurrent net 03 04,crc[%#x][%#x],cmd=%#x,data[%#x][%#x][%#x][%#x]",rcv_xor,crc_xor,msg->cmd,(msg->data[0]),(msg->data[1]),(msg->data[2]),(msg->data[3]) ) ;
                write_to_register(FPGA_CLEAR1_REG,0x02,0x02,sel_fpag);                  //更新寄存器,数据已读取
                //清除掉0x83
                write_to_register(FPGA_CONTROL1_REG,0x02,0x00,sel_fpag);                //!<使能发送
            }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 0 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                //BX_printf("\n 3/4 port_num : %d addr: %#x\n",port_num,msg->srcAdd);
                if(g_net_frame_seq==msg->msgSeq){
                    //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                }
            }
        }
    }


    if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x10){
        //read_from_register(RX_RAM_HIGH_REG,sel_fpag);//接收数据有效高字节
        read_from_register(RX_RAM_LOW_REG_56,sel_fpag);
        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_56] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0x30) << 4)) + 1;
        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
            //write_to_register(FPGA_CONTROL1_REG,0x04,0x04,sel_fpag);//!<使能发送
            read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_56,sel_fpag); //读取数据到MCU命令缓存中
            //phy_rx->rcv_len = eth_data_len;
            //!<计算除最后一位校验位以外的XOR值
            crc_xor = Utils::BCC((Ouint8 *)phy_rx, eth_data_len - 1);
            //!<接收的XOR校验值
            rcv_xor = phy_rx[eth_data_len - 1];
            msg = (PhyData_Type *)phy_rx;
            //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
            //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
            if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                if(rcv_xor == crc_xor){
                    if(msg->cmd == CMD_SEARCH_GROUP){
                        g_netport_recored1|=(1<<(2+sel_fpag*8));

                        if((msg->data[0] == 0x00)){
                            Search_concurrent_back_result(msg,1,sel_fpag,eth_data_len);
                        }
                    }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                        to_rcv_sure_cmd_39 |=(1<<(2+sel_fpag*8));
                    }
                    //write_to_register(FPGA_CLEAR1_REG,0x04,0x04,sel_fpag);               //更新寄存器,数据已读取
                    //清除掉0x83
                    //write_to_register(FPGA_CONTROL1_REG,0x04,0x00,sel_fpag);//!<使能发送

                    ret=1;
                    read_from_register(FPGA_STATE2_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                }
                write_to_register(FPGA_CLEAR1_REG,0x04,0x04,sel_fpag);               //更新寄存器,数据已读取
                //清除掉0x83
                write_to_register(FPGA_CONTROL1_REG,0x04,0x00,sel_fpag);//!<使能发送
            }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 1 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                if(g_net_frame_seq==msg->msgSeq){
                    //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                }

            }
        }
    }

    if (g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM > 6)
    {
        if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x40){
            //read_from_register(RX_RAM_HIGH_REG,sel_fpag);//接收数据有效高字节
            read_from_register(RX_RAM_LOW_REG_78,sel_fpag);
            eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_78] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0xc0) << 2)) + 1;
            if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                //write_to_register(FPGA_CONTROL1_REG,0x08,0x08,sel_fpag);//!<使能发送
                read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_78,sel_fpag);//读取数据到MCU命令缓存中
                //phy_rx->rcv_len = eth_data_len;
                //!<计算除最后一位校验位以外的XOR值
                crc_xor = Utils::BCC((Ouint8 *)phy_rx, eth_data_len - 1);
                //!<接收的XOR校验值
                rcv_xor = phy_rx[eth_data_len - 1];
                msg = (PhyData_Type *)phy_rx;
                //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
                //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
                if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                    if(rcv_xor == crc_xor){
                        if(msg->cmd == CMD_SEARCH_GROUP){
                            g_netport_recored1|=(1<<(3+sel_fpag*8));
                            if((msg->data[0] == 0x00)){
                                Search_concurrent_back_result(msg,1,sel_fpag,eth_data_len);
                            }
                        }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                            to_rcv_sure_cmd_39 |=(1<<(3+sel_fpag*8));
                        }


                        //write_to_register(FPGA_CLEAR1_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取

                        //清除掉0x83
                        //write_to_register(FPGA_CONTROL1_REG,0x08,0x00,sel_fpag);//!<使能发送

                        ret=1;
                        read_from_register(FPGA_STATE2_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                    }
                    write_to_register(FPGA_CLEAR1_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取
                    //清除掉0x83
                    write_to_register(FPGA_CONTROL1_REG,0x08,0x00,sel_fpag);//!<使能发送
                }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                    port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 1 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                    if(g_net_frame_seq==msg->msgSeq){
                        //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                    }

                }
            }
        }

        if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x01){
            //read_from_register(RX_RAM_HIGH_REG2,sel_fpag);//接收数据有效高字节
            read_from_register(RX_RAM_LOW_REG_910,sel_fpag);
            eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_910] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0x03) << 8)) + 1;
            if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                //write_to_register(FPGA_CONTROL3_REG,0x01,0x01,sel_fpag);//!<使能发送
                read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_910,sel_fpag);//读取数据到MCU命令缓存中
                //phy_rx->rcv_len = eth_data_len;
                //!<计算除最后一位校验位以外的XOR值
                crc_xor = Utils::BCC((Ouint8 *)phy_rx, eth_data_len - 1);
                //!<接收的XOR校验值
                rcv_xor = phy_rx[eth_data_len - 1];
                msg = (PhyData_Type *)phy_rx;
                //BX_printf("\n in deal_with_search_concurrent(09 10) cmd(%d)%d\n",msg->cmd,sel_fpag) ;
                //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
                //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
                if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                    if(rcv_xor == crc_xor){
                        if(msg->cmd == CMD_SEARCH_GROUP){
                            g_netport_recored1|=(1<<(4+sel_fpag*8));

                            if((msg->data[0] == 0x00)){
                                Search_concurrent_back_result(msg,2,sel_fpag,eth_data_len);
                            }
                        }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                            to_rcv_sure_cmd_39 |=(1<<(4+sel_fpag*8));
                        }
                        //write_to_register(FPGA_CLEAR1_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取

                        //清除掉0x83
                        //write_to_register(FPGA_CONTROL1_REG,0x08,0x00,sel_fpag);//!<使能发送

                        ret=1;
                        read_from_register(FPGA_STATE4_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                    }
                    write_to_register(FPGA_CLEAR2_REG,0x01,0x01,sel_fpag);             //更新寄存器,数据已读取
                    //清除掉0x93
                    //read_from_register(FPGA_CONTROL3_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                    //BX_printf("\n deal_with_search_concurrent 93(01)(%#x)%d\n",MCU_REG_func[sel_fpag][FPGA_CONTROL3_REG],sel_fpag)
                    write_to_register(FPGA_CONTROL3_REG,0x01,0x00,sel_fpag);//!<使能发送
                    //read_from_register(FPGA_CONTROL3_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                    //BX_printf("\n deal_with_search_concurrent 93(02)(%#x)%d\n",MCU_REG_func[sel_fpag][FPGA_CONTROL3_REG],sel_fpag)

                }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                    port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 2 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                    if(g_net_frame_seq==msg->msgSeq){
                        //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                    }

                }
            }
        }

        if (g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM > 10)
        {
            if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x04){
                //read_from_register(RX_RAM_HIGH_REG2,sel_fpag);//接收数据有效高字节
                read_from_register(RX_RAM_LOW_REG_1112,sel_fpag);
                eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_1112] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0x0c) << 6)) + 1;
                //回来的数据没有计入校验位，这里要加一，下同
                if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                    //write_to_register(FPGA_CONTROL3_REG,0x02,0x02,sel_fpag);//!<使能发送
                    read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1112,sel_fpag);//读取数据到MCU命令缓存中
                    //phy_rx->rcv_len = eth_data_len;
                    //!<计算除最后一位校验位以外的XOR值
                    crc_xor = Utils::BCC(phy_rx, eth_data_len - 1);
                    //!<接收的XOR校验值
                    rcv_xor = phy_rx[eth_data_len - 1];
                    msg = (PhyData_Type *)phy_rx;
                    //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
                    //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
                    if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                        if(rcv_xor == crc_xor){
                            if(msg->cmd == CMD_SEARCH_GROUP){
                                g_netport_recored1|=(1<<(5+sel_fpag*8));

                                if((msg->data[0] == 0x00)){
                                    Search_concurrent_back_result(msg,2,sel_fpag,eth_data_len);
                                }
                            }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                                to_rcv_sure_cmd_39 |=(1<<(5+sel_fpag*8));
                            }
                            //write_to_register(FPGA_CLEAR1_REG,0x02,0x02,sel_fpag);                  //更新寄存器,数据已读取

                            //清除掉0x83
                            //write_to_register(FPGA_CONTROL1_REG,0x02,0x00,sel_fpag);                //!<使能发送
                            ret=1;
                            read_from_register(FPGA_STATE4_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                        }
                        write_to_register(FPGA_CLEAR2_REG,0x02,0x02,sel_fpag);                  //更新寄存器,数据已读取
                        //清除掉0x83
                        write_to_register(FPGA_CONTROL3_REG,0x02,0x00,sel_fpag);                //!<使能发送
                    }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                        port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 2 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                        if(g_net_frame_seq==msg->msgSeq){
                            //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                        }
                    }
                }
            }

            if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x10){
                //read_from_register(RX_RAM_HIGH_REG2,sel_fpag);//接收数据有效高字节
                read_from_register(RX_RAM_LOW_REG_1314,sel_fpag);
                eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_1314] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0x30) << 4)) + 1;
                if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                    //write_to_register(FPGA_CONTROL3_REG,0x04,0x04,sel_fpag);//!<使能发送
                    read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1314,sel_fpag); //读取数据到MCU命令缓存中
                    //phy_rx->rcv_len = eth_data_len;
                    //!<计算除最后一位校验位以外的XOR值
                    crc_xor = Utils::BCC((Ouint8 *)phy_rx, eth_data_len - 1);
                    //!<接收的XOR校验值
                    rcv_xor = phy_rx[eth_data_len - 1];
                    msg = (PhyData_Type *)phy_rx;
                    //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
                    //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
                    if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                        if(rcv_xor == crc_xor){
                            if(msg->cmd == CMD_SEARCH_GROUP){
                                g_netport_recored1|=(1<<(6+sel_fpag*8));
                                if((msg->data[0] == 0x00)){
                                    Search_concurrent_back_result(msg,3,sel_fpag,eth_data_len);
                                }
                            }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                                to_rcv_sure_cmd_39 |=(1<<(6+sel_fpag*8));
                            }
                            //write_to_register(FPGA_CLEAR1_REG,0x04,0x04,sel_fpag);               //更新寄存器,数据已读取
                            //清除掉0x83
                            //write_to_register(FPGA_CONTROL1_REG,0x04,0x00,sel_fpag);//!<使能发送

                            ret=1;
                            read_from_register(FPGA_STATE4_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                        }
                        write_to_register(FPGA_CLEAR2_REG,0x04,0x04,sel_fpag);               //更新寄存器,数据已读取
                        //清除掉0x83
                        write_to_register(FPGA_CONTROL3_REG,0x04,0x00,sel_fpag);//!<使能发送
                    }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                        port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 3 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                        if(g_net_frame_seq==msg->msgSeq){
                            //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                        }

                    }
                }
            }

            if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x40){
                //read_from_register(RX_RAM_HIGH_REG2,sel_fpag);//接收数据有效高字节
                read_from_register(RX_RAM_LOW_REG_1516,sel_fpag);
                eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_1516] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0xc0) << 2)) + 1;
                if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                    //write_to_register(FPGA_CONTROL3_REG,0x08,0x08,sel_fpag);//!<使能发送
                    read_fpga_ram(phy_rx,0,eth_data_len,RX_RAM_1516,sel_fpag);//读取数据到MCU命令缓存中
                    //phy_rx->rcv_len = eth_data_len;
                    //!<计算除最后一位校验位以外的XOR值
                    crc_xor = Utils::BCC((Ouint8 *)phy_rx, eth_data_len - 1);
                    //!<接收的XOR校验值
                    rcv_xor = phy_rx[eth_data_len - 1];
                    msg = (PhyData_Type *)phy_rx;
                    //BX_printf("\n in deal_with_search_concurrent cmd(%d)%d\n",msg->cmd,sel_fpag) ;
                    //目前 仅仅针对 搜索帧  其它均按原来的处理方式进行处理
                    //if((rcv_xor == xor)&&(msg->Frame_data[0] == CMD_SEARCH_GROUP)&&(msg->Frame_data[1] == 0x00)){
                    if((msg->dstAddr == FPGA_DEFAULT_ADDR)&&(msg->cmd == CMD_SEARCH_GROUP /* || msg->cmd == CMD_RCV_BIND_GROUP*/)){
                        if(rcv_xor == crc_xor){
                            if(msg->cmd == CMD_SEARCH_GROUP){
                                g_netport_recored1|=(1<<(7+sel_fpag*8));
                                if((msg->data[0] == 0x00)){
                                    Search_concurrent_back_result(msg,3,sel_fpag,eth_data_len);
                                }
                            }else if(msg->cmd == CMD_RCV_BIND_GROUP){
                                to_rcv_sure_cmd_39 |=(1<<(7+sel_fpag*8));
                            }
                            //write_to_register(FPGA_CLEAR1_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取

                            //清除掉0x83
                            //write_to_register(FPGA_CONTROL1_REG,0x08,0x00,sel_fpag);//!<使能发送

                            ret=1;
                            read_from_register(FPGA_STATE4_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                        }
                        write_to_register(FPGA_CLEAR2_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取
                        //清除掉0x83
                        write_to_register(FPGA_CONTROL3_REG,0x08,0x00,sel_fpag);//!<使能发送
                    }else if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode)){
                        port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 3 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                        if(g_net_frame_seq==msg->msgSeq){
                            //g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                        }

                    }
                }
            }
        }
    }
    return  ret ;
}

//#endif







void fpga_manage::Rcv_data_from_eth(Ouint8 sel_fpag)
{
    //PHY_RX *phy_rx;
    Ouint8 data[FRAME_DATA_LEN];
    PhyData_Type *msg;
    Ouint8  eth_flag=0;                     //!<表示FPGA OUT口的数据更新标记
    Ouint8 group,port_num,crc_xor,rcv_xor;
    Ouint32 fpga_link_stat;
    Ouint16 eth_data_len;                //!<表示FPGA OUT口数据更新数据长度
    Ouint8 send = 0;
    bool fpga_multicast_mode =false;

    //    phy_rx = &g_phy_deal.phy_rx[PC_FPGA_SPI];

    //    if(phy_rx->rcv_flag == PHY_GF_VALID){
    //        return ;
    //    }


    //针对并发发送搜索帧进行 命令并发处理
    //#ifdef CONCURRENT_ENABLE
    //对命令进行并发处理  目前仅针对搜索帧
    deal_with_search_concurrent(sel_fpag);
    //read_from_register(FPGA_STATE2_REG);//FPGA状态寄存器[接收数据是否有效]
    //#endif


    //    phy_rx = &g_phy_deal.phy_rx[PC_FPGA_SPI];
    msg = (PhyData_Type *)(data);

    //获取网口接收到的数据长度  接收数据内部有效数据长度 高低字节

    read_from_register(FPGA_STATE2_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
    read_from_register(RX_RAM_HIGH_REG,sel_fpag);//接收数据有效高字节
    read_from_register(FPGA_STATE4_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
    read_from_register(RX_RAM_HIGH_REG2,sel_fpag);//接收数据有效高字节
    //!<表示网口 1,2 的 RX_RAM 区收到有效数据
    if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x01){
        read_from_register(RX_RAM_LOW_REG_12,sel_fpag);
        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_12] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0x03) << 8)) + 1;
        //回来的数据没有计入校验位，这里要加一，下同
        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
            //write_to_register(FPGA_CONTROL1_REG,0x01,0x01,sel_fpag);//!<使能发送(fpga set 1 by himself)
            read_fpga_ram(data,0,eth_data_len,RX_RAM_12,sel_fpag);//读取数据到MCU命令缓存中
            group = 0;
            eth_flag = 1;
        }
        //            BX_printf("\n Rcv_data_from_eth net 01 02,sel_fpag=%#x,eth_flag=%#x\n",sel_fpag,eth_flag) ;
        //!<计算除最后一位校验位以外的XOR值
        crc_xor = Utils::BCC(data, eth_data_len - 1);
        //!<接收的XOR校验值
        rcv_xor = data[eth_data_len - 1];

        if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){

            write_to_register(FPGA_CLEAR1_REG,0x01,0x01,sel_fpag);//更新寄存器,数据已读取
            //清除掉0x83
            write_to_register(FPGA_CONTROL1_REG,0x01,0x00,sel_fpag);//!<使能发送
        }

        //BX_printf("\n in Rcv_data_from_eth cmd(net 01 02) = %d(%d) \n",msg->cmd,sel_fpag) ;


        if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP) ){
            port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 0 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1

            if(msg->cmd == CMD_RCV_BIND_GROUP){
                to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
            }//else

            if(g_net_frame_seq==msg->msgSeq){
                g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
            }else{
                eth_flag=0;
                //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
            }

        }
        //PC发送的搜索帧
        else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
            if(msg->data[0] == 0x00){
                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 0 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                if(msg->reserved0){
                    if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                        port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                    }else{
                        port_num = (msg->reserved0 - 1);
                    }
                }
                update_eth_rcv_num(msg,port_num,sel_fpag);
            }
        }
    }else if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x04){                    //表示网口3,4的RX_RAM区MCU命令缓存中
        read_from_register(RX_RAM_LOW_REG_34,sel_fpag);
        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_34] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0x0c) << 6)) + 1;
        //回来的数据没有计入校验位，这里要加一，下同
        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
            //write_to_register(FPGA_CONTROL1_REG,0x02,0x02,sel_fpag);//!<使能发送
            read_fpga_ram(data,0,eth_data_len,RX_RAM_34,sel_fpag);//读取数据到MCU命令缓存中
            eth_flag = 1;
            group = 0;
        }

        //            BX_printf("\n Rcv_data_from_eth net 03 04 ,cmd = %#x len=%#x, dst=%#x,src=%#x\n",data[FRAME_CMD],eth_data_len,msg->dstAddr,msg->srcAdd) ;
        //!<计算除最后一位校验位以外的XOR值
        crc_xor = Utils::BCC(data, eth_data_len - 1);
        //!<接收的XOR校验值
        rcv_xor = data[eth_data_len - 1];


        if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
            write_to_register(FPGA_CLEAR1_REG,0x02,0x02,sel_fpag);             //更新寄存器,数据已读取
            //清除掉0x83
            write_to_register(FPGA_CONTROL1_REG,0x02,0x00,sel_fpag);//!<使能发送
        }
        //BX_printf("\n in Rcv_data_from_eth cmd(net 03 04) = %d(%d) \n",msg->cmd,sel_fpag) ;
        if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
            port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 0 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
            if(msg->cmd == CMD_RCV_BIND_GROUP){
                to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
            }//else

            if(g_net_frame_seq==msg->msgSeq){
                g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
            }else{
                eth_flag=0;
                //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
            }

        }
        //PC发送的搜索帧
        else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
            if(msg->data[0] == 0x00){
                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 0 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                if(msg->reserved0){
                    if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                        port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                    }else{
                        port_num = (msg->reserved0 - 1);
                    }
                }
                update_eth_rcv_num(msg,port_num,sel_fpag);
            }
        }
    }else if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x10){                    //!<表示网口 5,6 的 RX_RAM 区收到有效数据
        read_from_register(RX_RAM_LOW_REG_56,sel_fpag);
        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_56] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0x30) << 4)) + 1;
        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
            //write_to_register(FPGA_CONTROL1_REG,0x04,0x04,sel_fpag);//!<使能发送
            read_fpga_ram(data,0,eth_data_len,RX_RAM_56,sel_fpag); //读取数据到MCU命令缓存中
            eth_flag = 1;
            group = 1;              //!<第二组
        }
        //!<计算除最后一位校验位以外的XOR值
        crc_xor = Utils::BCC(data, eth_data_len - 1);
        //!<接收的XOR校验值
        rcv_xor = data[eth_data_len - 1];
        if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
            write_to_register(FPGA_CLEAR1_REG,0x04,0x04,sel_fpag);             //更新寄存器,数据已读取
            //清除掉0x83
            write_to_register(FPGA_CONTROL1_REG,0x04,0x00,sel_fpag);//!<使能发送
        }
        //BX_printf("\n in Rcv_data_from_eth cmd(net 05 06) = cmd=%#x(%d) ,len=%#x ,dst=%#x,src=%#x\n",msg->cmd,sel_fpag,eth_data_len,msg->dstAddr,msg->srcAdd) ;
        //            BX_printf("\n Rcv_data_from_eth net 05 06  rcv_xor=%#x, crc_xor = %#x,msg->reserved0=%#x,g_sync_netport_trans_mode=%#x,msg->cmd=%#x,g_net_frame_seq=%#x\n",
        //                      rcv_xor,rcv_xor,msg->reserved0,g_sync_netport_trans_mode,msg->cmd,g_net_frame_seq) ;
        if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
            port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 1 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
            if(msg->cmd == CMD_RCV_BIND_GROUP){
                to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
            }//else

            if(g_net_frame_seq==msg->msgSeq){
                g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
            }else{
                eth_flag=0;
                //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
            }

        }
        //PC发送的搜索帧
        else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
            if(msg->data[0] == 0x00){
                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 1 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                if(msg->reserved0){
                    if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                        port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                    }else{
                        port_num = (msg->reserved0 - 1);
                    }
                }
                update_eth_rcv_num(msg,port_num,sel_fpag);
            }
        }
    }else
    {
        if (g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM > 6)
        {

            if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x40){//!<表示网口 7,8 的 RX_RAM 区收到有效数据
                read_from_register(RX_RAM_LOW_REG_78,sel_fpag);
                eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_78] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG] & 0xc0) << 2)) + 1;
                if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                    //write_to_register(FPGA_CONTROL1_REG,0x08,0x08,sel_fpag);//!<使能发送
                    read_fpga_ram(data,0,eth_data_len,RX_RAM_78,sel_fpag);//读取数据到MCU命令缓存中
                    eth_flag = 1;
                    group = 1;
                }
                //!<计算除最后一位校验位以外的XOR值
                crc_xor = Utils::BCC(data, eth_data_len - 1);
                //!<接收的XOR校验值
                rcv_xor = data[eth_data_len - 1];
                //            msg = (PhyData_Type *)(data);
                if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
                    write_to_register(FPGA_CLEAR1_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取
                    //清除掉0x83
                    write_to_register(FPGA_CONTROL1_REG,0x08,0x00,sel_fpag);//!<使能发送
                }
                //BX_printf("\n in Rcv_data_from_eth cmd(net 07 08) = %d(%d) \n",msg->cmd,sel_fpag) ;
                //            BX_printf("\n Rcv_data_from_eth net 07 08\n") ;
                if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
                    port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 1 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1

                    if(msg->cmd == CMD_RCV_BIND_GROUP){
                        to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                    }//else

                    if(g_net_frame_seq==msg->msgSeq){
                        g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                    }else{
                        eth_flag=0;
                        //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                        //                    phy_rx->rcv_flag_ticks = G_timeTicks;
                    }

                }
                //PC发送的搜索帧
                else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
                    if(msg->data[0] == 0x00){
                        port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 1 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                        if(msg->reserved0){
                            if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                                port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                            }else{
                                port_num = (msg->reserved0 - 1);
                            }
                        }
                        update_eth_rcv_num(msg,port_num,sel_fpag);
                    }
                }
            }
            //have no fpg#endifa ram addr
            else if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x01){                    //表示网口9,10的RX_RAM区MCU命令缓存中
                read_from_register(RX_RAM_LOW_REG_910,sel_fpag);
                eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_910] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0x03) << 8)) + 1;
                //回来的数据没有计入校验位，这里要加一，下同
                if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                    //write_to_register(FPGA_CONTROL3_REG,0x01,0x01,sel_fpag);//!<使能发送
                    read_fpga_ram(data,0,eth_data_len,RX_RAM_910,sel_fpag);//读取数据到MCU命令缓存中
                    eth_flag = 1;
                    group = 2;
                }

                //                    BX_printf("\n Rcv_data_from_eth net 09 10 ,cmd = %#x len=%#x\n",data[FRAME_CMD],eth_data_len) ;
                //!<计算除最后一位校验位以外的XOR值
                crc_xor = Utils::BCC(data, eth_data_len - 1);
                //!<接收的XOR校验值
                rcv_xor = data[eth_data_len - 1];


                if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
                    write_to_register(FPGA_CLEAR2_REG,0x01,0x01,sel_fpag);             //更新寄存器,数据已读取
                    //清除掉0x93
                    /*read_from_register(FPGA_CONTROL3_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                                if((MCU_REG_func[sel_fpag][FPGA_CONTROL3_REG]&0xF0)!=0x00){
                                    BX_printf("\n in Rcv_data_from_eth(ERROR) cmd(net 09 10 01 )(93)(%#x)%d\n",MCU_REG_func[sel_fpag][FPGA_CONTROL3_REG],sel_fpag)
                                }*/

                    write_to_register(FPGA_CONTROL3_REG,0x01,0x00,sel_fpag);//!<使能发送
                    /*read_from_register(FPGA_CONTROL3_REG,sel_fpag);//FPGA状态寄存器[接收数据是否有效]
                                if((MCU_REG_func[sel_fpag][FPGA_CONTROL3_REG]&0xF0)!=0x00){
                                    BX_printf("\n in Rcv_data_from_eth(ERROR) cmd(net 09 10 02)(93)(%#x)%d\n",MCU_REG_func[sel_fpag][FPGA_CONTROL3_REG],sel_fpag)
                                }*/
                }
                //BX_printf("\n in Rcv_data_from_eth cmd(net 09 10) = %d(%d) \n",msg->cmd,sel_fpag) ;
                if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
                    port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 2 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1

                    if(msg->cmd == CMD_RCV_BIND_GROUP){
                        to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                    }//else

                    if(g_net_frame_seq==msg->msgSeq){
                        g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                    }else{
                        eth_flag=0;
                    }

                }
                //PC发送的搜索帧
                else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
                    if(msg->data[0] == 0x00){
                        port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 2 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                        if(msg->reserved0){
                            if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                                port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                            }else{
                                port_num = (msg->reserved0 - 1);
                            }
                        }
                        update_eth_rcv_num(msg,port_num,sel_fpag);
                    }
                }
            }else
            {
                if (g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM > 10)
                {

                    if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x04){                    //表示网口11,12的RX_RAM区MCU命令缓存中
                        read_from_register(RX_RAM_LOW_REG_1112,sel_fpag);
                        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_1112] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0x0c) << 6)) + 1;
                        //回来的数据没有计入校验位，这里要加一，下同
                        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                            //write_to_register(FPGA_CONTROL3_REG,0x02,0x02,sel_fpag);//!<使能发送
                            read_fpga_ram(data,0,eth_data_len,RX_RAM_1112,sel_fpag);//读取数据到MCU命令缓存中
                            eth_flag = 1;
                            group = 2;
                        }

                        //BX_printf("\n Rcv_data_from_eth net 11 12 ,cmd = %#x len=%#x\n",data[FRAME_CMD],eth_data_len) ;
                        //!<计算除最后一位校验位以外的XOR值
                        crc_xor = Utils::BCC(data, eth_data_len - 1);
                        //!<接收的XOR校验值
                        rcv_xor = data[eth_data_len - 1];


                        if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
                            write_to_register(FPGA_CLEAR2_REG,0x02,0x02,sel_fpag);             //更新寄存器,数据已读取
                            //清除掉0x83
                            write_to_register(FPGA_CONTROL3_REG,0x02,0x00,sel_fpag);//!<使能发送
                        }
                        //BX_printf("\n in Rcv_data_from_eth cmd(net 11 12) = %d(%d) \n",msg->cmd,sel_fpag) ;
                        if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
                            port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 2 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1

                            if(msg->cmd == CMD_RCV_BIND_GROUP){
                                to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                            }

                            if(g_net_frame_seq==msg->msgSeq){
                                g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                            }else{
                                eth_flag=0;
                                //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
                            }

                        }
                        //PC发送的搜索帧
                        else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
                            if(msg->data[0] == 0x00){
                                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 2 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                                if(msg->reserved0){
                                    if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                                        port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                                    }else{
                                        port_num = (msg->reserved0 - 1);
                                    }
                                }
                                update_eth_rcv_num(msg,port_num,sel_fpag);
                            }
                        }
                    }
                    else if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x10){                    //表示网口 13,14 的 RX_RAM 区收到有效数据
                        read_from_register(RX_RAM_LOW_REG_1314,sel_fpag);
                        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_1314] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0x30) << 4)) + 1;
                        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                            //write_to_register(FPGA_CONTROL3_REG,0x04,0x04,sel_fpag);//!<使能发送
                            read_fpga_ram(data,0,eth_data_len,RX_RAM_1314,sel_fpag); //读取数据到MCU命令缓存中
                            eth_flag = 1;
                            group = 3;              //!<第二组
                        }
                        //!<计算除最后一位校验位以外的XOR值
                        crc_xor = Utils::BCC(data, eth_data_len - 1);
                        //!<接收的XOR校验值
                        rcv_xor = data[eth_data_len - 1];
                        if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
                            write_to_register(FPGA_CLEAR2_REG,0x04,0x04,sel_fpag);             //更新寄存器,数据已读取
                            //清除掉0x83
                            write_to_register(FPGA_CONTROL3_REG,0x04,0x00,sel_fpag);//!<使能发送
                        }
                        //BX_printf("\n in Rcv_data_from_eth cmd(net 13 14) = %d(%d) \n",msg->cmd,sel_fpag) ;
                        //                    BX_printf("\n Rcv_data_from_eth net 13 14\n") ;
                        if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
                            port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 3 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                            if(msg->cmd == CMD_RCV_BIND_GROUP){
                                to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                            }//else

                            if(g_net_frame_seq==msg->msgSeq){
                                g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                            }else{
                                eth_flag=0;
                                //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
                            }

                        }
                        //PC发送的搜索帧
                        else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
                            if(msg->data[0] == 0x00){
                                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 3 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                                if(msg->reserved0){
                                    if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                                        port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                                    }else{
                                        port_num = (msg->reserved0 - 1);
                                    }
                                }
                                update_eth_rcv_num(msg,port_num,sel_fpag);
                            }
                        }
                    }
                    else if(MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x40){                    //表示网口 15,16 的 RX_RAM 区收到有效数据
                        read_from_register(RX_RAM_LOW_REG_1516,sel_fpag);
                        eth_data_len = (MCU_REG_func[sel_fpag][RX_RAM_LOW_REG_1516] | ((MCU_REG_func[sel_fpag][RX_RAM_HIGH_REG2] & 0xc0) << 2)) + 1;
                        if((eth_data_len > 0) && (eth_data_len <= RAM_MAX_LEN)){
                            //write_to_register(FPGA_CONTROL3_REG,0x08,0x08,sel_fpag);//!<使能发送
                            read_fpga_ram(data,0,eth_data_len,RX_RAM_1516,sel_fpag);//读取数据到MCU命令缓存中
                            eth_flag = 1;
                            group = 3;
                        }
                        //!<计算除最后一位校验位以外的XOR值
                        crc_xor = Utils::BCC(data, eth_data_len - 1);
                        //!<接收的XOR校验值
                        rcv_xor = data[eth_data_len - 1];
                        //                    msg = (PhyData_Type *)(data);
                        if((msg->cmd!=CMD_SEARCH_GROUP)||(msg->dstAddr != FPGA_DEFAULT_ADDR)){
                            write_to_register(FPGA_CLEAR2_REG,0x08,0x08,sel_fpag);//更新寄存器,数据已读取
                            //清除掉0x83
                            write_to_register(FPGA_CONTROL3_REG,0x08,0x00,sel_fpag);//!<使能发送
                        }
                        //BX_printf("\n in Rcv_data_from_eth cmd(net 15 16) = %d(%d) \n",msg->cmd,sel_fpag) ;
                        //                    BX_printf("\n Rcv_data_from_eth net 15 16\n") ;
                        if((rcv_xor == crc_xor)&&(msg->reserved0 == 0xff||g_sync_netport_trans_mode&&(msg->dstAddr == PC_DEFAULT_ADDR))&&(msg->cmd!= CMD_SEARCH_GROUP)){
                            port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 3 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                            if(msg->cmd == CMD_RCV_BIND_GROUP){
                                to_rcv_sure_cmd_39 |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                            }//else

                            if(g_net_frame_seq==msg->msgSeq){
                                g_fpga_ack_statue |= 1 << (port_num+sel_fpag*OUT_PORT_NUM - 1);//有回复的端口bit位置1
                            }else{
                                eth_flag=0;
                                //                    phy_rx->rcv_flag = PHY_GF_INVALID;
                                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
                            }

                        }
                        //PC发送的搜索帧
                        else if((rcv_xor == crc_xor)&&(msg->cmd== CMD_SEARCH_GROUP) && (msg->dstAddr == PC_DEFAULT_ADDR)){
                            if(msg->data[0] == 0x00){
                                port_num = ((((msg->srcAdd)>>8) & 0x30) >> 4) + 3 * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
                                if(msg->reserved0){
                                    if(msg->reserved0 > sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM){
                                        port_num = (msg->reserved0 - sel_fpag * g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM - 1);
                                    }else{
                                        port_num = (msg->reserved0 - 1);
                                    }
                                }
                                update_eth_rcv_num(msg,port_num,sel_fpag);
                            }
                        }
                    }
                }
            }
        }
    }
        




    if(eth_flag){
        //                msg = (PhyData_Type *)phy_rx->data;
        if((msg->dstAddr>=FPGA_DEFAULT_ADDR)&&(msg->dstAddr<=0xF00F)&&(msg->srcAdd<0xF000)&&(msg->msgSeq==0x66)){
            //针对接收卡回复进行特殊处理 目前针对亮度调节这一块 帧序号为66
            eth_flag=0;
            //                    phy_rx->rcv_flag = PHY_GF_INVALID;
        }
        //                BX_printf("\n") ;
        //                for(int mm=0; mm <eth_data_len;mm++ ){
        //                BX_printf(" %#x ",data[mm]) ;

        //                }
        //                BX_printf("\n") ;

        if((msg->dstAddr>=FPGA_DEFAULT_ADDR)&&(msg->dstAddr<=0xF00F)&&(msg->srcAdd<0xF000)&&(msg->msgSeq==0x67)){
            //针对接收卡回复进行特殊处理 目前针对调节这一块 帧序号为67
            g_send_para.rcv_back = 1;
            eth_flag=0;
            //                    phy_rx->rcv_flag = PHY_GF_INVALID;
        }

        //#ifdef CONCURRENT_ENABLE
        if((msg->cmd==CMD_SEARCH_GROUP)&&(msg->dstAddr == FPGA_DEFAULT_ADDR)){

            eth_flag=0;
            //                    phy_rx->rcv_flag = PHY_GF_INVALID;

            //#ifdef CONCURRENT_ENABLE
            //对命令进行并发处理  目前仅针对搜索帧
            deal_with_search_concurrent(sel_fpag);
            if((msg->dstAddr>=FPGA_DEFAULT_ADDR)&&(msg->dstAddr<=0xF00F)&&(msg->srcAdd<0xF000)&&(msg->msgSeq==0x67)){
                //针对接收卡回复进行特殊处理 目前针对调节这一块 帧序号为67
                g_send_para.rcv_back = 1;
            }
            //read_from_register(FPGA_STATE2_REG);//FPGA状态寄存器[接收数据是否有效]
            //#endif
        }
        //#endif



        //just for vmf
        /***************************************/

        if(/*(eth_data_len == 0x80 + 11)&&*/((msg->cmd==0xA0)||(msg->cmd==0x61))&&(msg->dstAddr==FPGA_DEFAULT_ADDR)){
            VMF_port_data_valid = 1;
            G_VMF_VALUE_back[0] = msg->cmd;
            int i;
            for(i=0;i<0x80+1;i++){//1(status)
                G_VMF_VALUE_back[i+1] = msg->data[i];

            }

            eth_flag=0;
        }
    }


    //if((eth_flag == 1)&&(phy_rx->rcv_flag == PHY_GF_INVALID)){//!<有新数据，更新参数
    if(eth_flag == 1){//!<有新数据，更新参数


        /***************************************/

        //此只针对PC
        if((data[7] == 0x00)&&(0==g_sync_netport_trans_mode)){
            port_num = ((data[3] & 0x30) >> 4) + group * 4 + 1;//获取端口号,PC从1开始计数，这里要加1
            data[7] = port_num+sel_fpag*OUT_PORT_NUM;                                 //!<接收卡返回默认为0，需要手动替换
            data[eth_data_len - 1] ^= data[7];//port_num;                 //!<因为替换的是0x00，这里直接把校验码异或一下就是新的校验码

            data[eth_data_len - 1] ^= data[3];//!<去掉该位异或值
            data[3] &= 0xcf; //!<端口号清零
            data[eth_data_len - 1] ^= data[3];//!<与新值异或

            //                phy_rx->rcv_flag = PHY_GF_VALID;
            //                phy_rx->rcv_flag_ticks = G_timeTicks;
            //                phy_rx->rcv_len = eth_data_len;
            send = 1;


        }else if((data[7] == 0xFF)||g_sync_netport_trans_mode){//!<广播模式


            Utils::_fpga_multicast_mutex.lock();
            fpga_multicast_mode = set_fpga_multicast_mode;
            fpga_link_stat = fpga_multicast_net;
            Utils::_fpga_multicast_mutex.unlock();

            if(fpga_multicast_mode == false){
                fpga_link_stat = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG]) | (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8)
        #if (defined OUTPUT_BOARD_2)
                        |\
                        (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG] << 16) | (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 24)
        #endif
                        ;
#if (defined OUTPUT_BOARD_2)
                int link_port = 0;
                for(int i = 0 ; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM*2 ; i++){
                    link_port = (i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM) ? i : (i - g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM + OUT_PORT_NUM) ;
                    if((fpga_link_stat >> link_port) & 0x01){
                        if(get_port_card_num(i)){
                            continue;
                        }else{
                            fpga_link_stat &= (~(1<<link_port));
                        }
                    }
                }
#else
                for(int i = 0 ; i < g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM ; i++){
                    if((fpga_link_stat >> i) & 0x01){
                        if(get_port_card_num(i)){
                            continue;
                        }else{
                            fpga_link_stat &= (~(1<<i));
                        }
                    }
                }
#endif

                //                    BX_printf("\n g_fpga_ack_statue : %#x  fpga_link_stat : %#x (ticks=%d)\n",g_fpga_ack_statue,fpga_link_stat,G_timeTicks);
            }

            if(g_fpga_ack_statue == fpga_link_stat){//!<所有链接的卡均已回复

                if(g_dataflow_flag == 1){
                    data[eth_data_len - 1] ^= data[2];//!<去掉该位异或值
                    data[eth_data_len - 1] ^= data[3];//!<去掉该位异或值
                    data[eth_data_len - 1] ^= data[7];//!<去掉该位异或值

                    data[2] = 0xfe; //!<
                    data[3] = 0x0f; //!<
                    data[7] = 0xff; //!<

                    data[eth_data_len - 1] ^= data[2];//!<与新值异或
                    data[eth_data_len - 1] ^= data[3];//!<与新值异或
                    data[eth_data_len - 1] ^= data[7];//!<去掉该位异或值

                    //                          Utils::_system_mutex.lock();
                    g_dataflow_flag = 0;
                    //                          Utils::_system_mutex.unlock();
                }else{

                    data[eth_data_len - 1] ^= data[2];//!<去掉该位异或值
                    data[eth_data_len - 1] ^= data[3];//!<去掉该位异或值
                    data[eth_data_len - 1] ^= data[7];//!<去掉该位异或值

                    data[2] = 0xff; //!<
                    data[3] = 0x0f; //!<
                    data[7] = 0xff; //!<

                    data[eth_data_len - 1] ^= data[2];//!<与新值异或
                    data[eth_data_len - 1] ^= data[3];//!<与新值异或
                    data[eth_data_len - 1] ^= data[7];//!<去掉该位异或值

                }

                //                    phy_rx->rcv_flag = PHY_GF_VALID;
                //                    phy_rx->rcv_flag_ticks = G_timeTicks;
                //                    phy_rx->rcv_len = eth_data_len;
                //g_fpga_ack_statue=2;
                send = 1;
                if(g_check_netport_trans_mode==1){//命令帧完成
                    g_fpga_ack_statue=0;
                    Utils::_system_mutex.lock();
                    g_check_netport_trans_mode=0;
                    Utils::_system_mutex.unlock();
                }
            }
        }else{
            data[eth_data_len - 1] ^= data[3];//!<去掉该位异或值
            data[3] &= 0xcf; //!<端口号清零
            data[eth_data_len - 1] ^= data[3];//!<与新值异或


            //                phy_rx->rcv_flag = PHY_GF_VALID;
            //                phy_rx->rcv_flag_ticks = G_timeTicks;
            //                phy_rx->rcv_len = eth_data_len;
            send = 1;
        } 

    }
    if(send){
        data_from_eth_len = eth_data_len;
        for(Oint32 i = 0; i < eth_data_len ; i++){
            data_from_eth[i] = data[i];
        }
    } 
}


#if 0
void fpga_manage::check_fpga_irq_status(Ouint8 sel_fpag)
{
    //优先检查 PFGA版本
    if(  (MCU_REG_func[sel_fpag][FPGA_INIT_OK] != 0x03)&&( MCU_REG_func[sel_fpag][FPGA_INIT_OK] != 0x02 )  ){
        return ;
    }
#if 1
    read_from_register(FPGA_STATE0_REG,sel_fpag);//读取FPGA状态寄存器
    //add by chendy
    read_from_register(FPGA_STATE2_REG,sel_fpag);//读取FPGA状态寄存器

    if(MCU_REG_func[sel_fpag][FPGA_STATE0_REG] & 0x20){
        if((g_change.sys_reg_flag[sel_fpag]==0)&&(pc_cmd_valid==0)){
            g_change.sys_reg_flag[sel_fpag]=1;

            //            BX_printf("\n sorry to here check irq timeout here\n ") ;
        }
    }/*else if(MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x04){
        if((g_change.sys_reg_flag[sel_fpag]==0)&&(pc_cmd_valid==0)){
            g_change.sys_reg_flag[sel_fpag]=1;

            BX_printf("\n sorry to here check irq timeout add\n ") ;
        }
    }*/
#endif
}
#endif

void fpga_manage::check_fpga_net_data_status(Ouint8 sel_fpag)
{
    //优先检查 PFGA版本
    if(  (MCU_REG_func[sel_fpag][FPGA_INIT_OK] != 0x03)&&( MCU_REG_func[sel_fpag][FPGA_INIT_OK] != 0x02 )  ){
        return ;
    }
#if 1
    read_from_register(FPGA_STATE2_REG,sel_fpag);//读取FPGA状态寄存器
    read_from_register(FPGA_STATE4_REG,sel_fpag);//读取FPGA状态寄存器

    if((MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x55) || (MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x55)){
        if((g_change.sys_reg_flag[sel_fpag]==0)){
            g_change.sys_reg_flag[sel_fpag]=1;

            //            BX_printf("\n sorry to here check irq timeout here !!! error !!!\n ") ;
        }
    }
#endif
}



/*!
*  @brief	reg_IRQ_Dealwith()
*  @param	none
*  @return	none
*  @note	none
*/

void fpga_manage::reg_IRQ_Dealwith(Ouint8 sel_fpag, Ouint8 mode)
{
    //int fd;
    //优先检查 PFGA版本
    if(  (MCU_REG_func[sel_fpag][FPGA_INIT_OK] != 0x03)&&( MCU_REG_func[sel_fpag][FPGA_INIT_OK] != 0x02 )  ){
        return ;
    }

    //check_fpga_irq(sel_fpag);

    //char val[1] = {0};
    Ouint8 value = 0 ;
    if(sel_fpag == FPGA_MASTER_VBYONE1){
        //value = *(unsigned short *)in_fpga1_irq_event ;
        BX_printf("reg_IRQ_Dealwith\n");
        // value = getGpioReadStatus(3, 20);
        value = fpga_ctl_int1_gpio_get();
        // printf("\n get value = %#x sel_fpga : %d \n ",value ,sel_fpag) ;
    }
    if(((value & 0x01)||(mode == 0x01))==  0x01){
        g_change.sys_reg_flag[sel_fpag] = 1;
        g_change.sys_fpga_check_net_flag[sel_fpag]=0;
    }else{
        g_change.sys_reg_flag[sel_fpag] = 0;
    }



#if 1
    // BX_printf("\n ==================reg_IRQ_Dealwith==================== \n") ;
    if(g_change.sys_reg_flag[sel_fpag] == 1){
        //IntMasterDisable();
        //        pthread_mutex_lock(&m_fpga_irq_event_mutex);
        g_change.sys_reg_flag[sel_fpag] = 0;
        //        pthread_mutex_unlock(&m_fpga_irq_event_mutex);
        //        BX_printf("\n\n\n yes ,i got the irq \n\n\n") ;
        //IntMasterEnable();
        //快闪 3秒
        //        G_fpga_irq_check_ticks=G_timeTicks;
        //        set_led_run_mode(1,300);  //!<快闪模式

        write_to_register(FPGA_STATE0_REG,0x20,0x00,sel_fpag);//清除中断
        read_from_register(FPGA_STATE0_REG,sel_fpag);//读取FPGA状态寄存器
        if(MCU_REG_func[sel_fpag][FPGA_STATE0_REG] & 0x40){//表明FPGA重新上电过 MCU需要清除该位
            write_to_register(FPGA_STATE0_REG,0x60,0x00,sel_fpag);//清除中断和上电标志

            //再去读一下版本
            read_from_register(FPGA_BYTE3_REG,sel_fpag);//版本 年,MCU自加2000
            if(!((MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]>=FPGA_VER_START_YEAR)&&
                 (MCU_REG_func[sel_fpag][FPGA_BYTE3_REG]<=FPGA_VER_END_YEAR))){
                MCU_REG_func[sel_fpag][FPGA_INIT_OK]=0;
                g_change.sys_fpga_delay_time[sel_fpag]=G_timeTicks;
                //                wait_fpga_communite_time=100;
            }

        }

        read_from_register(FPGA_STATE2_REG,sel_fpag);//读取FPGA状态寄存器
        read_from_register(FPGA_STATE4_REG,sel_fpag);//读取FPGA状态寄存器
        //接收数据到网络缓存区 表示网口有数据更新需要MCU去读
        // BX_printf("\n ==================Rcv_data_from_eth==================== \n") ;
        if((MCU_REG_func[sel_fpag][FPGA_STATE2_REG] & 0x55) || (MCU_REG_func[sel_fpag][FPGA_STATE4_REG] & 0x55)) {
                    //    BX_printf("\n yes get the eth data ....FPGA_STATE2_REG=%#x,FPGA_STATE4_REG=%#x\n") ;
            Rcv_data_from_eth(sel_fpag);
                        // BX_printf("\n yes get the eth data \n") ;
        }

        update_eth_state(sel_fpag);                  //更新网口参数
        //        check_fpga_irq_ticks = G_timeTicks;
    }/*else if((Utils:: getTimeSpace(check_fpga_irq_ticks)>5)&&(pc_cmd_valid==0)){
        //IntMasterDisable();
       check_fpga_irq_ticks = G_timeTicks;
        //IntMasterEnable();
//        check_fpga_irq_status(sel_fpag);
    }*/
    else if((pc_cmd_valid==1)&&(g_check_netport_trans_mode == 1)){
        if(g_change.sys_fpga_check_net_flag[sel_fpag] == 0){
            g_change.sys_fpga_check_net_para_ticks[sel_fpag] = G_timeTicks;
            g_change.sys_fpga_check_net_flag[sel_fpag]=1;
        }else if(g_change.sys_fpga_check_net_flag[sel_fpag]==1){
            if(Utils:: getTimeSpace(g_change.sys_fpga_check_net_para_ticks[sel_fpag])>1){
                check_fpga_net_data_status(sel_fpag);
                g_change.sys_fpga_check_net_flag[sel_fpag]=0;
            }
        }
    }

#endif

}


/*!
*  @brief	Brightness_hand_change()  ---上电手动调亮
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_hand_change(void)
{
    int value = 0;

    if(g_change.sys_Bri_rcv_change){

        //接收卡个数与变化则启动一次同步亮度设置
        g_change.sys_Bri_times = 0;
        g_change.sys_Bri_rcv_change = 0;
    }

    if(g_change.sys_Bri_times < 5){

        value = Brightness_hand_dealwith(1);
        ////手动调亮上电只调亮5次
        g_change.sys_Bri_times++;
        if((value == 0)&&(g_change.sys_Bri_times >= 5)){
            g_change.sys_Bri_times = 0;
        }

    }

}

/*!
*  @brief	Brightness_time_change()  ---定时调亮
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_time_change(void)
{
    Ouint32 time_data;
    Ouint32 offset;


    time_data = read_time.hour * 60 + read_time.minute;
    offset = time_data / BRIGHTNESS_TIME;
    //大于48组调亮值则取最后一个
    if(offset >= 48){
        offset = offset - 1;  ///使用最后的的
    }

    //亮度表格有变化
    if((g_Bri_table_change != offset)||(g_change.sys_Bri_rcv_change)){
        //当前系统亮度值
        g_change.sys_Bri_value = HalfHourValue[offset];
        //写入到寄存器区
        MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] = g_change.sys_Bri_value;
#if (defined OUTPUT_BOARD_2)
        MCU_REG_func[FPGA_MASTER_VBYONE2][0x40] = g_change.sys_Bri_value;
#endif
        //启动一次调亮
        Brightness_hand_dealwith(1);
        //后面补发2次，增加系统可靠性
        g_change.sys_Bri_times = 0;

        g_Bri_table_change = offset;

        //清除变化的标记
        if(g_change.sys_Bri_rcv_change){
            g_change.sys_Bri_rcv_change = 0;
        }

    }

    if(g_change.sys_Bri_times < 2){

        Brightness_hand_dealwith(1);
        ////手动调亮上电只调亮3次
        g_change.sys_Bri_times++;
    }


}

/*!
*  @brief	Brightness_auto_filter()  ---- 亮度值抗干扰处理
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_auto_filter(void)
{

    ////VMF的数值表有更新
    if(g_change.sys_VMF_data_valid){

        ////如果亮度传感器在线的话
        if(G_VMF_VALUE[0x31] == 0xFF){

            ////每次只减小一个等级
            if(g_change.sys_Bri_value < G_VMF_VALUE[0x34]){
                g_change.sys_Bri_value = g_change.sys_Bri_value + 1;
            }
            else {
                if(g_change.sys_Bri_value > G_VMF_VALUE[0x34]){
                    g_change.sys_Bri_value = g_change.sys_Bri_value - 1;
                }
            }

            /////越界判断
            if(g_change.sys_Bri_value == 0){
                g_change.sys_Bri_value = 1;
            }

            if(g_change.sys_Bri_value >= 17){
                g_change.sys_Bri_value = 16;
            }

            //写入到寄存器区
            MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] = g_change.sys_Bri_value;
#if (defined OUTPUT_BOARD_2)
            MCU_REG_func[FPGA_MASTER_VBYONE2][0x40] = g_change.sys_Bri_value;
#endif
        }

        g_change.sys_VMF_data_valid = 0;
    }

    if(g_change.fun_Bri_check_num == 10){//!<连续10次未能获取到亮度值，回到默认最大值
        g_change.sys_Bri_value = 16;
        MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] = g_change.sys_Bri_value;
        MCU_REG_func[FPGA_MASTER_VBYONE2][0x40] = g_change.sys_Bri_value;
        g_change.fun_Bri_check_num = 0;
    }

}

/*!
*  @brief	Brightness_auto_change()  ---自动调亮函数
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_auto_change(void)
{

    ////检查是否有多功能卡
    Brightness_check_VMF();
    ////从多功能卡获取亮度值
    Brightness_read_VMF_value();
    ////亮度值滤波处理
    Brightness_auto_filter();
    ////分发亮度值
    //启动一次调亮
    Brightness_hand_dealwith(1);

}

/*!
*  @brief	Brightness_check_VMF()  ---检查多功能卡
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_check_VMF(void)
{
    ////查找是否有无多功能卡，默认优先使用网口1上的多功能卡
    if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH0_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH1_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH2_VMF] > 0){
        ////只读取第三个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH3_VMF] > 0){
        ////只读取第四个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 1;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH4_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH5_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH6_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH7_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 2;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH8_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH9_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH10_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH11_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 3;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH12_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH13_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH14_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][ETH15_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 4;
    }
#if (defined OUTPUT_BOARD_2)
    else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH0_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH1_VMF] > 0){
        ////只读取第一个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH2_VMF] > 0){
        ////只读取第三个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH3_VMF] > 0){
        ////只读取第四个多功能卡上的亮度值
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 5;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH4_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH5_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH6_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH7_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 6;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH8_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH9_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH10_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH11_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 7;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH12_VMF] > 0){
        g_change.sys_VMF_port = SP_P1_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH13_VMF] > 0){
        g_change.sys_VMF_port = SP_P2_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH14_VMF] > 0){
        g_change.sys_VMF_port = SP_P3_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }else if(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][ETH15_VMF] > 0){
        g_change.sys_VMF_port = SP_P4_VMF_ADDR;
        g_change.sys_VMF_group = 8;
    }
#endif
    else{
        g_change.sys_VMF_port = 0x00;
        g_change.sys_VMF_group = 0;
    }

}


void fpga_manage::Send_read_VMF_data_cmd(void)
{
    Ouint8 xor_c,port_num;
    Ouint8 data_len,sel_fpga=FPGA_MASTER_VBYONE1;

    Ouint8 SEND_READ_VMF_CMD[19]={0x00,0x40,0x00,0xF0,0x10,0xBB,0x03,0x00,0x00,0x61,0x00,0x00,0x00,0x02,0x80,0x00,0x00,0x00,0x00};

    switch(g_change.sys_VMF_port){
    case SP_P1_VMF_ADDR:
        port_num = 0;
        break;
    case SP_P2_VMF_ADDR:
        port_num = 1;
        break;
    case SP_P3_VMF_ADDR:
        port_num = 2;
        break;
    case SP_P4_VMF_ADDR:
        port_num = 3;
        break;
    default:
        port_num = 0;
        break;
    }

    if(g_change.sys_VMF_group != 1){//第二组属于后四个网口
        port_num = port_num + (g_change.sys_VMF_group - 1) * 4;

        if(g_change.sys_VMF_group < 5){
            sel_fpga = FPGA_MASTER_VBYONE1;
        }else{
#if (defined OUTPUT_BOARD_2)
            sel_fpga = FPGA_MASTER_VBYONE2;
#endif
        }
    }



    SEND_READ_VMF_CMD[0] = g_change.sys_VMF_port & 0xFF;
    SEND_READ_VMF_CMD[1] = (g_change.sys_VMF_port >> 8) & 0xFF;

    xor_c = Utils::BCC((Ouint8 *)SEND_READ_VMF_CMD, 18);
    SEND_READ_VMF_CMD[18] = xor_c;//设置最后一位校验码

    data_len = 19 ;//- 1;
    Send_to_port(SEND_READ_VMF_CMD,data_len,port_num,sel_fpga);

}

void fpga_manage::VMF_data_back_result(void)
{
    //    PhyData_Type *msg;
    //    PHY_RX *phy_rx;
    //    Ouint8 xor_c,rcv_xor;
    Ouint16 n;


    if(VMF_port_data_valid){
        if((G_VMF_VALUE_back[1]==0x00)&&(g_change.sys_send_cmd_value==G_VMF_VALUE_back[0])){
            for(n = 0; n < 0x80; n++){
                G_VMF_VALUE[n] = G_VMF_VALUE_back[2 + n];
                //命令返回执行成功
                g_change.sys_VMF_data_valid = 1;
                g_change.sys_send_cmd_result = 1;
            }
        }else{
            MCU_REG_func[FPGA_MASTER_VBYONE1][0x55] = MCU_REG_func[FPGA_MASTER_VBYONE1][0x55] + 1;

            //命令执行异常需要重发
            g_change.sys_search_result = 2;
        }
    }

#if 0
    phy_rx = &g_phy_deal.phy_rx[PC_FPGA_SPI];

    //默认从机模式
    if(phy_rx->rcv_flag == PHY_GF_VALID){
        //帧解析
        msg = (PHY_HEAD *)phy_rx->data;
        //!<计算除最后一位校验位以外的XOR值
        xor_c = Utils::BCC((Ouint8 *)phy_rx->data, phy_rx->rcv_len - 1);
        //!<接收的XOR校验值
        rcv_xor = phy_rx->data[phy_rx->rcv_len - 1];
        if(rcv_xor == xor_c){
            //命令帧被处理
            //!<返回接收到的数据
            //检查命令返回结果是否执行成功
            if((msg->Frame_data[0] == g_change.sys_send_cmd_value)&&(msg->Frame_data[1] == 0x00)){
                //命令返回执行成功
                g_change.sys_VMF_data_valid = 1;
                g_change.sys_send_cmd_result = 1;

                //读取VMF返回的80个字节数据
                for(n = 0; n < 0x80; n++){
                    G_VMF_VALUE[n] = msg->Frame_data[2 + n];
                }

            }
            else{
                //命令执行异常需要重发
                g_change.sys_send_cmd_result = 2;
            }

        }else{
            //!<帧出错
            MCU_REG_func[FPGA_MASTER_VBYONE1][0x55] = MCU_REG_func[FPGA_MASTER_VBYONE1][0x55] + 1;

            //命令执行异常需要重发
            g_change.sys_search_result = 2;
        }
        //MCU_CMD_RX_flag.cmd_valid = 0;
        phy_rx->rcv_flag = PHY_GF_INVALID;
    }
#endif
}

/*!
*  @brief	Brightness_VMF_run 等待VMF返回命令
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_VMF_run(void)
{

    //处理FPGA中断
    reg_IRQ_Dealwith(0,0);
    reg_IRQ_Dealwith(1,0);
    //再检查网口缓存区数据
    //Check_eth_CMD_cache();
    //接收命令处理
    VMF_data_back_result();

}

/*!
*  @brief	Brightness_check_VMF()  ---检查多功能卡
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_read_VMF_value(void)
{
    Ouint32 run_flag;
    Ouint32 run_state;
    Ouint32 time_delay;

    ////是否有无多功能卡
    if(g_change.sys_VMF_port > 0){
        run_flag = 1;
    }
    else{
        run_flag = 0;
    }

    //默认起始状态
    run_state = 0;

    while(run_flag){


        //循环进入不同的状态
        switch(run_state){
        case 0:{
            //读取VMF卡数据
            Send_read_VMF_data_cmd();
            ////获取当前时间值
            time_delay = G_timeTicks;

            g_change.sys_send_cmd_result = 0;
            //RAM读命令
            g_change.sys_send_cmd_value = 0x61;
            //数据先无效
            g_change.sys_VMF_data_valid = 0;

            run_state = 1;
            VMF_port_data_valid = 0;
            break;
        }
        case 1:{
            //等待VMF数据收到
            Brightness_VMF_run();
            if(g_change.sys_send_cmd_result==1){
                //退出当前循环
                run_flag = 0;
                run_state = 0;
            }else if((g_change.sys_send_cmd_result != 0)||((G_timeTicks - time_delay) >= 35)){

                //退出当前循环
                run_flag = 0;
                run_state = 0;
                g_change.fun_Bri_check_num++;//!<计数+1
            }


            break;
        }
        default:{

            run_flag = 0;
        }

        }

    }

}

/*!
*  @brief	dealwith_onoff()
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::dealwith_onoff(void)
{
    Ouint8 i;

    //if(g_fpga_change.sys_screen_state == ScreenOff)
    //if(on_off_status == 1)
    //{
    for(i=0;i<GroupNum;i++)
    {
        if(on_flag[i] == 1)
        {
            if((read_time.hour == OnHour[i]) && (read_time.minute == OnMinute[i]))
            {
                //write_to_register(0x00,0x04,0x00);
                SCREEN_fpgactrl_status(SCREEN_LIGHT);

                on_flag[i] = 0;
                on_off_status = 0;
                Power_ctrl_reset();

            }
        }
    }
    //}else if(g_fpga_change.sys_screen_state == ScreenOn)
    //else if(on_off_status == 0)
    //{
    for(i=0;i<GroupNum;i++)
    {
        if(off_flag[i] == 1)
        {
            if((read_time.hour == OffHour[i]) && (read_time.minute == OffMinute[i]))
            {
                //write_to_register(0x00,0x04,0x04);
                SCREEN_fpgactrl_status(SCREEN_BLACK);

                off_flag[i] = 0;
                on_off_status = 1;
                Power_ctrl_reset();

            }
        }
    }
    //}

    if(read_time.date != check_date)//日期不同时全部刷新
    {
        for(i=0;i<GroupNum;i++)
        {
            on_flag[i] = 1;
            off_flag[i] = 1;
        }
        check_date = read_time.date;
    }

}

/*!
*  @brief	Brightness_task()
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Brightness_task(void)
{

    if((G_timeTicks - g_change.sys_Bri_task_time) >= BRI_TASK_CHECK_TIME){


        switch(g_BrightnessMode){
        case 0x10:
        case 0x00:{  ///手动调亮
            Brightness_hand_change();
            break;
        }
        case 0x11:
        case 0x01:{  ///定时调亮
            Brightness_time_change();
            break;
        }
        case 0x02:{  ///自动调亮
            Brightness_auto_change();
            break;
        }
        default:{
        }
        }

        g_change.sys_Bri_task_time = G_timeTicks;
    }

}



//fun
/*!
*  @brief	Extension_function()
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Extension_function(void)
{

    //查看亮度表格是否变化
    if(g_change.sys_Bri_change){
        record_bright_change();

        //清楚运行标记
        g_change.sys_Bri_change = 0;
    }

    //定时调亮与自动调亮调度
    if(g_change.sys_Bri_task){
        //无此函数
        //Brightness_task();
    }


    //  //定时开关机调度
    //  if(ChangeBright_flag == 1)
    //  {
    //    //定时/自动调亮
    //    FPGA_message_deal();
    //    //if(g_change.sys_FPGA_line_flag == 1)
    //    //{
    //      cascade_send_deal();
    //      seach_cascade_slave();
    //      Check_Cascade_TX_cache();
    //    //}
    //  }


    //周期检查级联发送卡

    if(MCU_REG_func[FPGA_MASTER_VBYONE1][0x42] == 0x01){
        dealwith_onoff();
    }



}





//fun
/*!
*  @brief	转发到具体某个网口
*  @param	none
*  @return	none
*  @note	none
*/
void fpga_manage::Send_to_port(Ouint8* eth_cach,Ouint16 data_len,Ouint16 port_num,Ouint8 sel_fpag)
{
    Ouint16 reg_len;
    Ouint8 tempL,tempH;
    //Ouint8 test_buf[128];
    //memset(test_buf,0x00,128);
    reg_len = data_len - 1;//!<硬件会自动加一，所以写入寄存器需要减一

    tempL = reg_len & 0x00ff;
    tempH = (reg_len & 0x0f00)>>8;

    wait_fpga_send_ready(port_num,sel_fpag);

    if(port_num < 8){
        write_to_register(FPGA_CONTROL2_REG,0xff,1<<port_num,sel_fpag);//!<判断发送到哪个网口
    }else if(port_num < 16){
        write_to_register(FPGA_CONTROL4_REG,0xff,1<<(port_num-8),sel_fpag);//!<判断发送到哪个网口
    }

    //BX_printf("\n send to port %d \n",port_num + 1 + sel_fpag * 16);

    switch(port_num+1){ //!<端口号从零开始计数，但网口从一开始，所以这里要加一
    case 1:
    case 2:
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_12,sel_fpag);//写入RAM中
        //read_fpga_ram(test_buf,0,data_len,TX_RAM_12);//回读测试是否正确写入
        write_to_register(TX_RAM_LOW_REG_12, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG, 0x03,tempH,sel_fpag);
        write_to_register(FPGA_CLEAR1_REG,0xf0,0x10,sel_fpag);//!<使能发送
        //清除掉0x83
        //        write_to_register(FPGA_CONTROL1_REG,0x01,0x00,sel_fpag);//!<使能发送
        break;
    case 3:
    case 4:
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_34,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_34, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG, 0x0c,tempH<<2,sel_fpag);
        write_to_register(FPGA_CLEAR1_REG,0xf0,0x20,sel_fpag);//!<使能发送
        //清除掉0x83
        //        write_to_register(FPGA_CONTROL1_REG,0x02,0x00,sel_fpag);//!<使能发送
        break;
    case 5:
    case 6:
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_56,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_56, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG, 0x30,tempH<<4,sel_fpag);
        write_to_register(FPGA_CLEAR1_REG,0xf0,0x40,sel_fpag);//!<使能发送

        //清除掉0x83
        //        write_to_register(FPGA_CONTROL1_REG,0x04,0x00,sel_fpag);//!<使能发送
        break;
    case 7:
    case 8:
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_78,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_78, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG, 0xc0,tempH<<6,sel_fpag);
        write_to_register(FPGA_CLEAR1_REG,0xf0,0x80,sel_fpag);//!<使能发送

        //清除掉0x83
        //        write_to_register(FPGA_CONTROL1_REG,0x08,0x00,sel_fpag);//!<使能发送
        break;
    case 9:
    case 10:
        // //
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_910,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_910, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG2, 0x03,tempH,sel_fpag);
        write_to_register(FPGA_CLEAR2_REG,0xf0,0x10,sel_fpag);//!<使能发送

        //清除掉0x93
        //        write_to_register(FPGA_CONTROL3_REG,0x01,0x00,sel_fpag);//!<使能发送
        break;
    case 11:
    case 12:
        // //
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_1112,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_1112, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG2, 0x0c,tempH<<2,sel_fpag);
        write_to_register(FPGA_CLEAR2_REG,0xf0,0x20,sel_fpag);//!<使能发送
        break;
    case 13:
    case 14:
        // //
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_1314,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_1314, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG2, 0x30,tempH<<4,sel_fpag);
        write_to_register(FPGA_CLEAR2_REG,0xf0,0x40,sel_fpag);//!<使能发送
        break;
    case 15:
    case 16:
        // //
        write_fpga_ram(eth_cach,0,data_len,TX_RAM_1516,sel_fpag);//写入RAM中
        write_to_register(TX_RAM_LOW_REG_1516, 0xff,tempL,sel_fpag);
        write_to_register(TX_RAM_HIGH_REG2, 0xc0,tempH<<6,sel_fpag);
        write_to_register(FPGA_CLEAR2_REG,0xf0,0x80,sel_fpag);//!<使能发送
        break;
    default:
        break;
    }
}




//fun
/*!
*  @brief	发送搜索卡命令
*  @param	data:网口连接状态
*               port_num:端口号
*               type:0:搜索命令 1:亮度值写入 2:亮度值有效
*  @return	none
*  @note	none
*/
void fpga_manage::check_error_rcv_search_card_cmd(Ouint32 port_num,Ouint8 sel_fpag,Ouint32 screen_id, Ouint32 config_id, Ouint8 config_id_enable)
{
    Ouint8 crc_xor,addr;
    Ouint8 ret = 0;
    Ouint8 reg_addr;
    Ouint8  check_error_search_cmd[]={0xFE,0x0F,0x00,0xF0,0x10,0xAA,0xFF,0x00,0x00,0x10,
                                      0x00,0x00,
                                      0x00,
                                      0x00,0x00,
                                      0x00,0x00,
                                      //config file id
                                      0x00,0x00,0x00,0x00,
                                      0xff,
                                      0x00,
                                      //device id
                                      0x00,0x00,0x00,0x00,
                                      0x00,0x00,
                                      0x00};//网口搜索卡命令

    //if(data != 0){
    switch(port_num){
    case 0:
    case 4:
    case 8:
    case 12:
        addr = 0x0F;
        break;
    case 1:
    case 5:
    case 9:
    case 13:
        addr = 0x1F;
        break;
    case 2:
    case 6:
    case 10:
    case 14:
        addr = 0x2F;
        break;
    case 3:
    case 7:
    case 11:
    case 15:
        addr = 0x3F;
        break;
    default:
        addr = 0x0F;
        break;
    }
    check_error_search_cmd[1] = addr;
    check_error_search_cmd[7] = port_num + 1;
    check_error_search_cmd[16] = config_id_enable &0x01;
    check_error_search_cmd[17] = screen_id & 0xFF;
    check_error_search_cmd[18] = ((screen_id >> 8) & 0xFF);
    check_error_search_cmd[19] = ((screen_id >> 16) & 0xFF);
    check_error_search_cmd[20] = ((screen_id >> 24) & 0xFF);

    check_error_search_cmd[23] = config_id & 0xFF;
    check_error_search_cmd[24] = ((config_id >> 8) & 0xFF);
    check_error_search_cmd[25] = ((config_id >> 16) & 0xFF);
    check_error_search_cmd[26] = ((config_id >> 24) & 0xFF);

    switch(port_num){
    case 0:
    case 1:
        ret = 0;
        reg_addr =FPGA_CONTROL1_REG;
        break;
    case 2:
    case 3:
        ret = 1;
        reg_addr =FPGA_CONTROL1_REG;
        break;
    case 4:
    case 5:
        ret = 2;
        reg_addr =FPGA_CONTROL1_REG;
        break;
    case 6:
    case 7:
        ret = 3;
        reg_addr =FPGA_CONTROL1_REG;
        break;
    case 8:
    case 9:
        ret = 0;
        reg_addr =FPGA_CONTROL3_REG;
        break;
    case 10:
    case 11:
        ret = 1;
        reg_addr =FPGA_CONTROL3_REG;
        break;
    case 12:
    case 13:
        ret = 2;
        reg_addr =FPGA_CONTROL3_REG;
        break;
    case 14:
    case 15:
        ret = 3;
        reg_addr =FPGA_CONTROL3_REG;
        break;
    default:
        break;
    }

    write_to_register(reg_addr,(1<<ret),0x00,sel_fpag);

    crc_xor = Utils::BCC((Ouint8 *)check_error_search_cmd, sizeof(check_error_search_cmd) - 1);
    check_error_search_cmd[sizeof(check_error_search_cmd) - 1] = crc_xor;
    Send_to_port(check_error_search_cmd,sizeof(check_error_search_cmd),port_num,sel_fpag);

     /*BX_printf("\nsending ......\n");
        for(int i = 0 ; i < sizeof(check_error_search_cmd) ;i++){
                BX_printf(" 0x%02x ",check_error_search_cmd[i]);

        }
                BX_printf("\n");*/ 

}

void fpga_manage::Send_rcv_card_cmd(Ouint32 port_num,Ouint8 type,Ouint8 sel_fpag)
{
    Ouint8 crc_xor,addr;

    //if(data != 0){
    switch(port_num){
    case 0:
    case 4:
    case 8:
    case 12:
        addr = 0x0F;
        break;
    case 1:
    case 5:
    case 9:
    case 13:
        addr = 0x1F;
        break;
    case 2:
    case 6:
    case 10:
    case 14:
        addr = 0x2F;
        break;
    case 3:
    case 7:
    case 11:
    case 15:
        addr = 0x3F;
        break;
    default:
        addr = 0x0F;
        break;
    }


    if(type == 0){//search cmd
        SEARCH_CARD_BUF[1] = addr;
        SEARCH_CARD_BUF[7] = port_num + 1;
        crc_xor = Utils::BCC((Ouint8 *)SEARCH_CARD_BUF, 14);
        SEARCH_CARD_BUF[14] = crc_xor;
        Send_to_port(SEARCH_CARD_BUF,sizeof(SEARCH_CARD_BUF),port_num,sel_fpag);
    }else if(type == 1){//brightness
        SEND_BRI_ETH_CMD[1] = addr;
        SEND_BRI_ETH_CMD[18] = MCU_REG_func[FPGA_MASTER_VBYONE1][0x40] * 16 - 1;
        crc_xor = Utils::BCC((Ouint8 *)SEND_BRI_ETH_CMD, 19);
        SEND_BRI_ETH_CMD[19] = crc_xor;
        Send_to_port(SEND_BRI_ETH_CMD,sizeof(SEND_BRI_ETH_CMD),port_num,sel_fpag);
    }else if(type == 2){//write brightness to reg
        SEND_BRI_ETH_REG[1] = addr;
        crc_xor = Utils::BCC((Ouint8 *)SEND_BRI_ETH_REG, 14);
        SEND_BRI_ETH_REG[14] = crc_xor;
        Send_to_port(SEND_BRI_ETH_REG,sizeof(SEND_BRI_ETH_REG),port_num,sel_fpag);
    }else if(type == 3){//save brightness
        SEND_BRI_SAVE_CMD[1] = addr;
        //SEND_BRI_SAVE_CMD[2] = data;
        crc_xor = Utils::BCC((Ouint8 *)SEND_BRI_SAVE_CMD, 12);
        SEND_BRI_ETH_REG[12] = crc_xor;
        Send_to_port(SEND_BRI_SAVE_CMD,sizeof(SEND_BRI_SAVE_CMD),port_num,sel_fpag);
    }
    //}

}





//fun
/*!
* @brief   CHECK_search_cmd_status()
* search cmd
* @param 	NONE
* @return	NONE
* @note
*/
void fpga_manage::CHECK_search_cmd_status(void)
{
    //对当前的搜索帧命令的回复情况进行判断
    //Ouint8 fpga1=0,fpga2=1;
    //g_netport_recored1  (低字节bit31表示当前已发送 允许查询) (低字节bit30 0 表示先查偶数 再查奇数)
    //g_netport_recored1 (bit0--bit7 fpga1 ack)(bit8---15 fapg2 ack)
    //g_netport_recored FPGA_MASTER_VBYONE1
    //高字节bit0--bit15表示当前网口发送网口置1表示之前发送过  FPGA1
    //高字节bit16--bit32表示当前网口发送网口置1表示之前发送过  FPG2A2

    if(g_netport_recored1&((Ouint32)(1<<31))){
        //当前有搜索帧发送 可以查询
        if(g_netport_recored1&(1<<30)){
            //先查询奇数次
            if((g_netport_recored1&(1<<(0+0)))==0 ){//no ack
                //FPGA1
                if(g_netport_recored&(1<<(0+1))){//port1
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x66] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x67] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x66],0x66,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+0))){//port0
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x64] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x65] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x68] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x64],0x64,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

            if((g_netport_recored1&(1<<(8+0)))==0 ){//no ack
#if (defined OUTPUT_BOARD_2)
                //FPGA2
                if(g_netport_recored&(1<<(16+1))){//port1
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x66] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x67] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x66],0x66,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+0))){//port0
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x64] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x65] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x68] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x64],0x64,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
#endif
            }


            if((g_netport_recored1&(1<<(0+1)))==0 ){//no ack
                //FPGA1
                if(g_netport_recored&(1<<(0+3))){//port3
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6E] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6F] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x72] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6E],0x6E,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+2))){//port2
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x70] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6C],0x6C,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

            if((g_netport_recored1&(1<<(8+1)))==0 ){//no ack
#if (defined OUTPUT_BOARD_2)
                //FPGA2
                if(g_netport_recored&(1<<(16+3))){//port3
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6E] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6F] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x72] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6E],0x6E,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+2))){//port2
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x70] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6C],0x6C,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
#endif
            }


            if((g_netport_recored1&(1<<(0+2)))==0 ){
                //FPGA1
                if(g_netport_recored&(1<<(0+5))){//port5
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x234] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x235] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x236] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x234],0x234,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+4))){//port4
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x230] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x231] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x232] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x230],0x230,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

            if((g_netport_recored1&(1<<(8+2)))==0 ){
#if (defined OUTPUT_BOARD_2)
                //FPGA2
                if(g_netport_recored&(1<<(16+5))){//port5
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x234] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x235] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x236] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x234],0x234,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+4))){//port4
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x230] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x231] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x232] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x230],0x230,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
#endif
            }

            //4
            if(((g_netport_recored1&(1<<(0+3)))==0) ){
                //FPGA1
                if(g_netport_recored&(1<<(0+7))){//port7
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23C],0x23C,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+6))){//port6
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x238] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x239] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x238],0x238,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }


            if((g_netport_recored1&(1<<(8+3)))==0 ){
#if (defined OUTPUT_BOARD_2)
                //FPGA2
                if(g_netport_recored&(1<<(16+7))){//port7
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23C],0x23C,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+6))){//port6
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x238] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x239] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x238],0x238,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
#endif
            }
            /****************************************************************/
            //fpga1
            if(((g_netport_recored1&(1<<(0+4)))==0) ){//no ack
                if(g_netport_recored&(1<<(0+9))){//port9
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x284] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x285] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x286] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x284],0x284,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+8))){//port8
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x280] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x281] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x282] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x280],0x280,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
            if(((g_netport_recored1&(1<<(0+5)))==0) ){//no ack
                if(g_netport_recored&(1<<(0+11))){//port11
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28C],0x28C,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+10))){//port10
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x288] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x289] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x288],0x288,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
            if(((g_netport_recored1&(1<<(0+6)))==0) ){//no ack
                if(g_netport_recored&(1<<(0+13))){//port13
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x294] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x295] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x296] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x294],0x294,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+12))){//port12
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x290] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x291] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x292] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x290],0x290,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
            if(((g_netport_recored1&(1<<(0+7)))==0) ){//no ack
                if(g_netport_recored&(1<<(0+15))){//port15
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29C],0x29C,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+14))){//port14
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x298] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x299] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x298],0x298,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
            /***************************************************************/
#if (defined OUTPUT_BOARD_2)
            //fpga2
            if(((g_netport_recored1&(1<<(8+4)))==0) ){//no ack
                if(g_netport_recored&(1<<(16+9))){//port9
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x284] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x285] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x286] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x284],0x284,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+8))){//port8
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x280] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x281] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x282] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x280],0x280,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
            if(((g_netport_recored1&(1<<(8+5)))==0) ){//no ack
                if(g_netport_recored&(1<<(16+11))){//port11
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28C],0x28C,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+10))){//port10
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x288] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x289] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x288],0x288,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
            if(((g_netport_recored1&(1<<(8+6)))==0) ){//no ack
                if(g_netport_recored&(1<<(16+13))){//port13
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x294] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x295] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x296] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x294],0x294,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+12))){//port12
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x290] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x291] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x292] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x290],0x290,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
            if(((g_netport_recored1&(1<<(8+7)))==0) ){//no ack
                if(g_netport_recored&(1<<(16+15))){//port15
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29C],0x29C,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+14))){//port14
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x298] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x299] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x298],0x298,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
#endif
            /**************************************************************/

        }else{
            if((g_netport_recored1&(1<<0))==0 ){//no ack
                if(g_netport_recored&(1<<(0+0))){//port0
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x64] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x65] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x68] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x64],0x64,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+1))){//port1
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x66] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x67] = 0  ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x66],0x66,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
#if (defined OUTPUT_BOARD_2)
            //FPGA2
            if((g_netport_recored1&(1<<(8+0)))==0 ){//no ack
                if(g_netport_recored&(1<<(16+0))){//port0
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x64] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x65] = 0 ; MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x68] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x64],0x64,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+1))){//port1
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x66] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x67] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x66],0x66,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
#endif

            if((g_netport_recored1&(1<<(0+1)))==0 ){//no ack(fpga1)
                if(g_netport_recored&(1<<(0+2))){//port2
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x70] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6C],0x6C,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+3))){//port3
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6E] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6F] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x72] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x6E],0x6E,5,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
#if (defined OUTPUT_BOARD_2)
            //FPGA2
            if((g_netport_recored1&(1<<(8+1)))==0 ){
                if(g_netport_recored&(1<<(16+2))){//port2
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x70] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6C],0x6C,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+3))){//port3
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6E] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6F] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x72] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x6E],0x6E,5,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
#endif

            if((g_netport_recored1&(1<<(0+2)))==0 ){//no ack(fgpa1)
                if(g_netport_recored&(1<<(0+4))){//port4
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x230] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x231] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x232] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x230],0x230,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+5))){//port5
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x234] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x235] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x236] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x234],0x234,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
#if (defined OUTPUT_BOARD_2)
            //FPGA2
            if((g_netport_recored1&(1<<(8+2)))==0 ){
                if(g_netport_recored&(1<<(16+4))){//port4
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x230] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x231] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x232] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x230],0x230,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+5))){//port5
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x234] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x235] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x236] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x234],0x234,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
#endif

            //4
            if((g_netport_recored1&(1<<(0+3)))==0 ){//no ack(fgpa1)
                //FPGA1
                if(g_netport_recored&(1<<(0+6))){//port6
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x238] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x239] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x238],0x238,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+7))){//port7
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x23C],0x23C,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

#if (defined OUTPUT_BOARD_2)
            //4
            if((g_netport_recored1&(1<<(8+3)))==0 ){
                //FPGA2
                if(g_netport_recored&(1<<(16+6))){//port6
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x238] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x239] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x238],0x238,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+7))){//port7
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x23C],0x23C,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
#endif

            //
            /**************************************************/
            if((g_netport_recored1&(1<<(0+4)))==0 ){//no ack(fgpa1)
                //FPGA1
                if(g_netport_recored&(1<<(0+8))){//port8
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x280] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x281] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x282] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x280],0x280,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+9))){//port9
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x284] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x285] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x286] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x284],0x284,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

            if((g_netport_recored1&(1<<(0+5)))==0 ){//no ack(fgpa1)
                //FPGA1
                if(g_netport_recored&(1<<(0+10))){//port10
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x288] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x289] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x288],0x288,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+11))){//port11
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28c] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28d] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28e] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x28c],0x28c,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

            if((g_netport_recored1&(1<<(0+6)))==0 ){//no ack(fgpa1)
                //FPGA1
                if(g_netport_recored&(1<<(0+12))){//port12
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x290] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x291] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x292] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x290],0x290,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+13))){//port13
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x294] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x295] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x296] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x294],0x294,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }
            if((g_netport_recored1&(1<<(0+7)))==0 ){//no ack(fgpa1)
                //FPGA1
                if(g_netport_recored&(1<<(0+14))){//port14
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x298] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x299] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x298],0x298,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }else if(g_netport_recored&(1<<(0+15))){//port15
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29C] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1][0x29C],0x29C,3,PARA_RAM,FPGA_MASTER_VBYONE1);
                }
            }

            /********************************************************************************/

#if (defined OUTPUT_BOARD_2)
            if((g_netport_recored1&(1<<(4+8)))==0 ){//no ack(fgpa2)
                //FPGA2
                if(g_netport_recored&(1<<(16+8))){//port8
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x280] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x281] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x282] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x280],0x280,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+9))){//port9
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x284] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x285] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x286] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x284],0x284,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }

            if((g_netport_recored1&(1<<(5+8)))==0 ){//no ack(fgpa2)
                //FPGA2
                if(g_netport_recored&(1<<(16+10))){//port10
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x288] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x289] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x288],0x288,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+11))){//port11
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28c] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28d] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28e] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x28c],0x28c,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }

            if((g_netport_recored1&(1<<(6+8)))==0 ){//no ack(fgpa2)
                //FPGA2
                if(g_netport_recored&(1<<(16+12))){//port12
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x290] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x291] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x292] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x290],0x290,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+13))){//port13
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x294] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x295] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x296] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x294],0x294,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
            if((g_netport_recored1&(1<<(7+8)))==0 ){//no ack(fgpa2)
                //FPGA2
                if(g_netport_recored&(1<<(16+14))){//port14
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x298] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x299] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29A] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x298],0x298,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }else if(g_netport_recored&(1<<(16+15))){//port15
                    MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29C] = 0 ;MCU_RAM_PARA_func[1][0x29D] = 0 ;MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29E] = 0 ;
                    write_fpga_ram(&MCU_RAM_PARA_func[FPGA_MASTER_VBYONE2][0x29C],0x29C,3,PARA_RAM,FPGA_MASTER_VBYONE2);
                }
            }
#endif
        }
    }

    g_netport_recored=0;
    g_netport_recored1=0;
}


Ouint8 fpga_manage::check_vbo_status(Ouint8 sel_fpag)
{
    Ouint8 vbo_status[8],i;
    Ouint8 m = 0;


    //每800ms读取一次
    if(Utils::getTimeSpace(g_change.sys_check_vbo_status_ticks[sel_fpag])  >= 10){

        if(fpga_vbo_status[sel_fpag] == 0x00){
            for(i=0;i<8;i++){
                vbo_status[i]=0x00;
                read_from_register(FPGA_VBO_REG,sel_fpag);//读取FPGA状态寄存器
                vbo_status[i]=MCU_REG_func[sel_fpag][FPGA_VBO_REG];
            }

            for(i=0;i<8;i++){
                if((vbo_status[i]&0x1C)!=0x1C){
                    break;
                }
            }

            if(i!=8){
                for(int k=0;k<8;k++){
                    if((vbo_status[k]&0x1C)!=0x1C){
                        m++;
                    }
                }

                if(m<=3){
                    i=8;
                }
#if 0
                read_from_register(FPGA_STATE_REG_03,sel_fpag);//读取FPGA状态寄存器
                read_from_register(FPGA_STATE0_REG,sel_fpag);//读取FPGA状态寄存器
                read_from_register(FPGA_CLEAR_REG,sel_fpag);//读取FPGA状态寄存器
                read_from_register(FPGA_STATE1_REG,sel_fpag);//读取FPGA状态寄存器
                read_from_register(FPGA_STATE3_REG,sel_fpag);//读取FPGA状态寄存器

                if(sel_fpag == FPGA_MASTER_VBYONE1){
                    BX_printf("\n check_vbo_status[OUT1-16],(R28[%#x,%#x,%#x,%#x,%#x,%#x,%#x,%#x] \n",
                              vbo_status[0],vbo_status[1],vbo_status[2],vbo_status[3],
                            vbo_status[4],vbo_status[5],vbo_status[6],vbo_status[7]) ;

                    BX_printf("\n check_vbo_status[OUT1-16],(R03=%#x,R16=%#x,R17=%#x,R80=%#x,R90=%#x) \n",
                              MCU_REG_func[sel_fpag][FPGA_STATE_REG_03],MCU_REG_func[sel_fpag][FPGA_STATE0_REG],
                              MCU_REG_func[sel_fpag][FPGA_CLEAR_REG],MCU_REG_func[sel_fpag][FPGA_STATE1_REG],
                              MCU_REG_func[sel_fpag][FPGA_STATE3_REG]) ;
                }else{
                    BX_printf("\n check_vbo_status[OUT17-32],(R28[%#x,%#x,%#x,%#x,%#x,%#x,%#x,%#x] \n",
                              vbo_status[0],vbo_status[1],vbo_status[2],vbo_status[3],
                            vbo_status[4],vbo_status[5],vbo_status[6],vbo_status[7]) ;
                    BX_printf("\n check_vbo_status[OUT17-32],(R03=%#x,R16=%#x,R17=%#x,R80=%#x,R90=%#x) \n",
                              MCU_REG_func[sel_fpag][FPGA_STATE_REG_03],MCU_REG_func[sel_fpag][FPGA_STATE0_REG],
                              MCU_REG_func[sel_fpag][FPGA_CLEAR_REG],MCU_REG_func[sel_fpag][FPGA_STATE1_REG],
                              MCU_REG_func[sel_fpag][FPGA_STATE3_REG]) ;
                }
#endif

            }

            if(i!=8){
                fpga_vbo_status[sel_fpag] = 0x01;
                write_to_register(FPGA_STATE_REG_03,0xC0,0x00,sel_fpag);
                fpga_vbo_check_setup[sel_fpag]=0x00;
            }
        }else{
            if(fpga_vbo_check_setup[sel_fpag] == 0x00){
                write_to_register(FPGA_STATE_REG_03,0x40,0x40,sel_fpag);
#if 0
                for(i=0;i<8;i++){
                    vbo_status[i]=0x00;
                    read_from_register(FPGA_STATE0_REG,sel_fpag);//读取FPGA状态寄存器
                    vbo_status[i]=MCU_REG_func[sel_fpag][FPGA_STATE0_REG];
                }

                for(i=0;i<8;i++){
                    if((vbo_status[i]&0x1C)!=0x1C){
                        break;
                    }
                }
#endif
                fpga_vbo_check_setup[sel_fpag] = 0x01;
                fpga_vbo_check_times[sel_fpag] = 0x00;

            }else if(fpga_vbo_check_setup[sel_fpag] == 0x01){
                read_from_register(FPGA_STATE0_REG,sel_fpag);
                fpga_vbo_check_times[sel_fpag]++;
                if( (MCU_REG_func[sel_fpag][FPGA_STATE0_REG]&0x08) == 0x08){
                    if(fpga_vbo_check_times[sel_fpag]>=10*100){
                        write_to_register(FPGA_STATE_REG_03,0x80,0x80,sel_fpag);
                        fpga_vbo_status[sel_fpag] = 0x00;
                    }

                }else{
                    write_to_register(FPGA_STATE_REG_03,0x80,0x80,sel_fpag);
                    fpga_vbo_status[sel_fpag] = 0x00;
                }
            }
        }


        g_change.sys_check_vbo_status_ticks[sel_fpag]=G_timeTicks;
    }

    return fpga_vbo_status[sel_fpag];
}




//fun
/*!
* @brief   SEARCH_card_cmd()
*
* @param 	NONE
* @return	NONE
* @note
*/
void fpga_manage::Search_Card_Cmd(void)
{
    Ouint32 /*time_delay,*/ret,turn;
    Ouint16 wlan_state[2];
    Ouint32 id_device = 0x00;

    Ouint8 i;

    //判断是否允许发送搜索帧
    if(((MCU_REG_func[FPGA_MASTER_VBYONE1][0] & 0x08) == 0x08)
        #if (defined OUTPUT_BOARD_2)
            ||( (MCU_REG_func[FPGA_MASTER_VBYONE2][0] & 0x08) == 0x08 )
        #endif
            ){

        g_change.sys_search_check_time = G_timeTicks;
        //BX_printf("\n search card stop !! \n");
        //PC禁止发送搜索帧
        return;

    }


    if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03){
        wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
    }else{
        wlan_state[0] = 0x00;
    }
#if (defined OUTPUT_BOARD_2)
    if(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] == 0x03){
        wlan_state[1] = (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];
    }else{
        wlan_state[1] = 0x00;
    }
#endif


    //每800ms读取一次
    if(Utils::getTimeSpace(g_change.sys_search_check_time)  >= SEARCH_ORDER_DELAY){

        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE1);//读取FPGA状态寄存器
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE1);//读取FPGA状态寄存器

#if (defined OUTPUT_BOARD_2)
        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE2);//读取FPGA状态寄存器
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE2);//读取FPGA状态寄存器
#endif


        //wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
        //wlan_state[1] = 0x0000;//(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];

        if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03){
            wlan_state[0] = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
        }else{
            wlan_state[0] = 0x00;
        }
#if (defined OUTPUT_BOARD_2)
        if(MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] == 0x03){
            wlan_state[1] = (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE3_REG] << 8) | MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE1_REG];
        }else{
            wlan_state[1] = 0x00;
        }
#endif

        //BX_printf("\n fpga1 wlan state : %#x, fpga2 wlan state : %#x\n",wlan_state[0],wlan_state[1]);
        //g_change.sys_data_in_line=0x0F;
        //相当于命令处理空闲
        if(g_change.sys_data_in_line == 0x0F){

            //多个网口都不在的话
            if((wlan_state[0] == 0x00)
        #if (defined OUTPUT_BOARD_2)
                    &&(wlan_state[1] == 0x00)
        #endif
                    ){
                //不用运行搜索卡命令
                g_change.sys_search_task = 0;
                g_change.sys_search_check_time = G_timeTicks;
            }
            else{
                //进入搜索命令回复等待装
                g_change.sys_search_task = 1;
                g_change.sys_search_state = 0;
            }
        }
        else{

            g_change.sys_search_task = 0;
            //退出时重新计数
            g_change.sys_search_check_time = G_timeTicks;

            //BX_printf("\n wlan busy!! \n");
        }



    }
    //#ifdef CONCURRENT_ENABLE
    //CONCURRENT_ENABLE    并发模式使能
    //SINGLE_SHOT_ENABLE   单发模式使能
    if(Timeout_flag){
        id_device = device_id;
    }

    if(g_change.sys_search_task){
        turn = g_change.sys_search_times % 2;//!<奇数轮次还是偶数轮次
        g_change.sys_search_times++;

        CHECK_search_cmd_status();

        Ouint8 config_id_enable = 0;
        config_id_enable = 0;//p_rcvRecovery->recovery_files.size();

        //BX_printf("\n (start send search cmd)fpga1 wlan state : %#x, fpga2 wlan state : %#x\n",wlan_state[0],wlan_state[1]);

        if(turn == 0){//!<同连接下，优先0、2、4、6
            for(ret=0;ret<(g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM/2);ret++){
                for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){
                    if( ((wlan_state[i]>>(2*ret))&0x01) == 1){

                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);

                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif


                        //Send_rcv_card_cmd(2*ret,0,i);
                        check_error_rcv_search_card_cmd(2*ret,i,0,id_device,(config_id_enable?1:0));

                        g_netport_recored1|=(1<<31);//允许查询
                        g_netport_recored1&=0xBFFF;//表示当前偶数优先
                        //标记当前发送的网口
                        g_netport_recored|=(1<<((2*ret)+16*(i)));

                        //                          BX_printf("\n search send turn=%#x ,i=%#x card=%d \n",turn,i,2*ret+1) ;

                    }else if(((wlan_state[i]>>(2*ret+1))&0x01) == 1){

                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);
                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif

                        //Send_rcv_card_cmd(2*ret+1,0,i);
                        check_error_rcv_search_card_cmd(2*ret+1,i,0,id_device,(config_id_enable?1:0));

                        g_netport_recored1|=(1<<31);//允许查询
                        g_netport_recored1&=0xBFFF;//表示当前偶数优先
                        //标记当前发送的网口
                        g_netport_recored|=(1<<((2*ret+1)+16*(i)));
                        //                          BX_printf("\n search send turn=%#x ,i=%#x card=%d \n",turn,i,2*ret+2) ;
                    }
                }
            }

        }else{//!<同连接下，优先1、3、5、7
            for(ret=0;ret<(g_Global->OVP_CONTROL_OUT_EACH_CARD_NET_NUM/2);ret++){
                for(i=0;i<g_Global->OVP_CONTROL_OUT_NUM;i++){
                    if( ((wlan_state[i]>>(2*ret+1))&0x01) == 1){

                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);
                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif

                        //Send_rcv_card_cmd(2*ret+1,0,i);
                        check_error_rcv_search_card_cmd(2*ret+1,i,0,id_device,(config_id_enable?1:0));

                        g_netport_recored1|=(1<<31);//允许查询
                        g_netport_recored1|=(1<<30);//表示当前偶数优先
                        //标记当前发送的网口

                        g_netport_recored|=(1<<(2*ret+1+16*(i)));
                        //                          BX_printf("\n search send turn=%#x ,i=%#x card=%d \n",turn,i,2*ret+2) ;
                    }else if( ((wlan_state[i]>>(2*ret))&0x01) == 1){

                        //
                        //发现市场返回一台长时间运行后出现0x83寄存器异常造成网口通讯阻塞
                        if(ret == 0 || ret == 1 || ret == 2 || ret == 3){
                            write_to_register(FPGA_CONTROL1_REG,(1<<ret),0x00,i);
                        }
#if (defined OUTPUT_BOARD_2)
                        else if(ret == 4 || ret == 5 || ret == 6 || ret == 7){
                            write_to_register(FPGA_CONTROL3_REG,(1<<(ret-4)),0x00,i);
                        }
#endif

                        //Send_rcv_card_cmd(2*ret,0,i);
                        check_error_rcv_search_card_cmd(2*ret,i,0,id_device,(config_id_enable?1:0));

                        g_netport_recored1|=(1<<31);//允许查询
                        g_netport_recored1|=(1<<30);//表示当前偶数优先
                        //标记当前发送的网口
                        g_netport_recored|=(1<<(2*ret+16*(i)));
                        //                          BX_printf("\n search send turn=%#x ,i=%#x card=%d \n",turn,i,2*ret+1) ;
                    }
                }
            }
        }
        g_change.sys_search_check_time=G_timeTicks;
        g_change.sys_search_task = 0;
    }
    //#else


    //#endif
}





//fun
/*!
* @brief
* @param 	NONE
* @return	NONE
* @note
*/
Ouint8 fpga_manage::get_fpga_status(void)
{
    //if(MCU_REG[FPGA_INIT_OK] == 0x01 || MCU_REG[FPGA_INIT_OK] == 0x02){
    if((((MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03)&&(fpga_init_step[FPGA_MASTER_VBYONE1] == FPGA_VBO_INIT_S7)&&(check_fpga_phy_status[FPGA_MASTER_VBYONE1] == FPGA_PHY_INIT_END))
    #if (defined OUTPUT_BOARD_2)
        &&(
            (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] == 0x03)&&(fpga_init_step[FPGA_MASTER_VBYONE2] == FPGA_VBO_INIT_S7)&&(check_fpga_phy_status[FPGA_MASTER_VBYONE2] == FPGA_PHY_INIT_END))
    #endif
        )&&(
                ((MCU_REG_func[FPGA_MASTER_VBYONE1][0] & 0x08) == 0x00)
            #if (defined OUTPUT_BOARD_2)
                &&
                ((MCU_REG_func[FPGA_MASTER_VBYONE2][0] & 0x08) == 0x00)
            #endif
                ) ){
        return 1;
    }
    return 0;
}




void fpga_manage::set_lcd_change_flag(void)
{
    g_lcd_change[0] = 3;
    g_lcd_change[1] = 3;

    //BX_printf("\n\n\n   monitor change start!!!   \n\n");
}

void fpga_manage::set_9022_para(int i)
{
    if(g_lcd_change[i] == 3){







    }
}


//fun
/*!
* @brief Check_search_card()
*
* @param 	NONE
* @return	NONE
* @note
*/
void fpga_manage::Check_search_card(void)
{
    //发送搜索卡命令(当PC不通讯时)
    if((pc_cmd_valid==0)&&get_fpga_status()){
        //        if((g_power_open_running == 0) || (g_power_close_running == 0)){//!<断电上电过程中暂停
        check_vbo_status(FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        check_vbo_status(FPGA_MASTER_VBYONE2);
#endif
        //if((rcv_locksend_over < OVP_RCV_LOCK_ACT_ATONCE)&&(rcv_unlocksend_over < OVP_RCV_LOCK_ACT_ATONCE)){
            Search_Card_Cmd();
        //}

        // rxc_lock_set();
#if 0
        if(g_RAM_IN_MCU[MCU_PARA7_BITS_INFO]&SET_BIT(REV_PARA_SAVE_BIT)
                == SET_BIT(REV_PARA_SAVE_BIT)){
            Search_new_rev_card();
        }else if((MCU_REG[2] & 0x10) == 0x10){
            g_RAM_IN_MCU[MCU_PARA7_BITS_INFO]|=SET_BIT(REV_PARA_SAVE_BIT);
            write_to_register(0x02,0x10,0x00,FPGA_MASTER_NEAR_VBYEON);
        }
#endif
        //扩展功能，定时调亮，自动调亮，定时开关机等
        //Extension_function();


        check_wlanonline_state();

        //        }
    }else{
        if(Utils::getTimeSpace(pc_cmd_time)>SEARCH_ORDER_DELAY){//300
            //            BX_printf("\n start to send search card \n") ;
            pc_cmd_valid = 0;
            g_netport_recored=0;
        }
        //禁止FPGA信号检测
        //g_change.sys_resolution_check_time = G_timeTicks;

    }
}

/*!
* @brief   SCREEN_black_light_status()
*  当前屏的黑屏这屏状态
* @param 	type   0--black   1--light
* @return	NONE
* @note
*/
void fpga_manage::SCREEN_fpgactrl_status(enum SCREEN_status status){
#ifdef OUTPUT_LEDNET
    switch(status){
    case SCREEN_BLACK://黑屏
        write_to_register(0x00,0x04,0x04,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(0x00,0x04,0x04,FPGA_MASTER_VBYONE2);
#endif
        break;

    case SCREEN_LIGHT://亮屏
        write_to_register(0x00,0x04,0x00,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(0x00,0x04,0x00,FPGA_MASTER_VBYONE2);
#endif
        break;

    case SCREEN_UNLOCK://解锁屏
        write_to_register(0x00,0x02,0x00,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(0x00,0x02,0x00,FPGA_MASTER_VBYONE2);
#endif

        break;

    case SCREEN_LOCK://锁屏
        write_to_register(0x00,0x02,0x02,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(0x00,0x02,0x02,FPGA_MASTER_VBYONE2);
#endif
        break;
    case ENABLE_LCD://使能LCD
        write_to_register(0x03,0x20,0x20,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(0x03,0x20,0x20,FPGA_MASTER_VBYONE2);
#endif
        break;
    case DISENABLE_LCD:
        write_to_register(0x03,0x20,0x00,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(0x03,0x20,0x00,FPGA_MASTER_VBYONE2);
#endif
        break;
    case VBY_DECODE_STATUS:
        read_from_register(FPGA_STATE0_REG,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        read_from_register(FPGA_STATE0_REG,FPGA_MASTER_VBYONE2);
#endif
        break;
#if 0
    case DSP_RESET_ING:
        write_to_register(FPGA_CLEAR_REG,0x20,0x20,FPGA_MASTER_VBYONE1);
        write_to_register(FPGA_CLEAR_REG,0x20,0x20,FPGA_MASTER_VBYONE2);
        break;
    case DSP_RESET_ING_1:
        write_to_register(FPGA_CLEAR_REG,0x20,0x20,FPGA_MASTER_VBYONE1);
        break;
    case DSP_RESET_OK:
        write_to_register(FPGA_CLEAR_REG,0x20,0x00,FPGA_MASTER_VBYONE1);
        write_to_register(FPGA_CLEAR_REG,0x20,0x00,FPGA_MASTER_VBYONE2);
        break;
    case DSP_RESET_OK_1:
        write_to_register(FPGA_CLEAR_REG,0x20,0x00,FPGA_MASTER_VBYONE1);
        break;
    case DSP_RESET_OK_2:
        //            write_to_register(FPGA_CLEAR_REG,0x20,0x00,FPGA_MASTER_NEAR_VBYEON);

        break;
#endif
    case VBYONE_NO_DIV_MODE:
        write_to_register(FPGA_CLEAR_REG,0x01,0x00,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(FPGA_CLEAR_REG,0x01,0x00,FPGA_MASTER_VBYONE2);
#endif

        //BX_printf("\n VBYONE_NO_DIV_MODE \n") ;
        break;
    case VBYONE_SPLICE_MODE:
        write_to_register(FPGA_CLEAR_REG,0x01,0x01,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        write_to_register(FPGA_CLEAR_REG,0x01,0x01,FPGA_MASTER_VBYONE2);
#endif

        //BX_printf("\n VBYONE_SPLICE_MODE \n") ;
        break;
    default:break;
    }
#endif
}


/*!
* @brief   SCREEN_black_light_status()
*  当前屏的黑屏这屏状态
* @param 	type   0--black   1--light
* @return	NONE
* @note
*/
#if 1
void fpga_manage::SCREEN_fpgactrl_status2(enum SCREEN_status status,Ouint8 sel_fpag){
#ifdef OUTPUT_LEDNET
    switch(status){
    case CHECK_FPGA_PHY_RESET:
        write_to_register(FPGA_CLEAR_REG,0x08,0x08,sel_fpag);
        break;
    case CHECK_FPGA_PHY_OK:
        write_to_register(FPGA_CLEAR_REG,0x08,0x00,sel_fpag);
        break;
    case ENABLE_LCD:
        write_to_register(/*0x03*/FPGA_STATE_REG_03,0x20,0x20,sel_fpag);
        break;
    case SCREEN_BLACK:
        write_to_register(0x00,0x04,0x04,sel_fpag);
        break;

    default:break;
    }
#endif
}
#endif



Ouint8 fpga_manage::set_output_status(void)
{

    if(get_fpga_status() == 0){

        return 0;
    }

    //if(SPLIT_8_to_16(p_ram0_u8,OPTION_INFO_OUTPUT)){
    //  SCREEN_fpgactrl_status(SCREEN_BLACK);
    // }else{
    SCREEN_fpgactrl_status(SCREEN_LIGHT);
    // }

    return 1;
}

Ouint8 fpga_manage::set_fpga_bri_val(void)
{
    /*if( ((MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] != 0x03)&&(fpga_init_step[FPGA_MASTER_VBYONE1] == FPGA_VBO_INIT_S7)&&(check_fpga_phy_status[FPGA_MASTER_VBYONE1] == FPGA_PHY_INIT_END))
         #if (defined OUTPUT_BOARD_2)
            ||
            (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] != 0x03)&&(fpga_init_step[FPGA_MASTER_VBYONE2] == FPGA_VBO_INIT_S7)&&(check_fpga_phy_status[FPGA_MASTER_VBYONE2] == FPGA_PHY_INIT_END)
        #endif
           ){
        return 0;
    }*/

    if(get_fpga_status() == 0){

        return 0;
    }
    Brightness_hand_dealwith(1);
    return 1;
}





Ouint8 fpga_manage::set_fpga_lcd(void)
{


    if(get_fpga_status() == 0){

        return 0;
    }

    G32_mcu_set_net_para(FPGA_MASTER_VBYONE1);
    write_fpga_ram(MCU_RAM_PARA_func[FPGA_MASTER_VBYONE1],0,1024,PARA_RAM,FPGA_MASTER_VBYONE1);
    write_to_register(0x02,0x01,0x01,FPGA_MASTER_VBYONE1);//update reg

    return 1;
}



void fpga_manage::set_led_para_deal(void)
{
    //    Ouint8 *p_ram0_u8 = (Ouint8 *)(OvpRamPara::p_ovprampara_config->ovp_ram.ovpG3ram0);

    /*if( (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] != 0x03)
        #if (defined OUTPUT_BOARD_2)
            ||\
            (MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_INIT_OK] != 0x03)
        #endif
           ){
        return ;
    }*/

    if(get_fpga_status() == 0){

        return ;
    }

    if(g_set_led_para==1){
        if(g_set_led_setup == 0){
            SCREEN_fpgactrl_status(SCREEN_BLACK);
            //            SCREEN_fpgactrl_status(DISENABLE_LCD);

            set_led_para_ticks = G_timeTicks ;
            Utils::_led_para_init_mutex.lock();
            g_set_led_setup = 1;
            Utils::_led_para_init_mutex.unlock();
            return ;
        }else if(g_set_led_setup == 1){
            if((Utils::getTimeSpace(set_led_para_ticks) > 10)){
                set_led_para_ticks = G_timeTicks;
                SCREEN_fpgactrl_status(DISENABLE_LCD);
                Utils::_led_para_init_mutex.lock();
                g_set_led_setup = 2;
                //                g_set_led_para = 0;
                Utils::_led_para_init_mutex.unlock();
            }
            return ;
        }else if(g_set_led_setup == 2){
            if((Utils::getTimeSpace(set_led_para_ticks) > 30)){
                set_led_para_ticks = G_timeTicks;
                Utils::_led_para_init_mutex.lock();
                g_set_led_setup = 0;
                g_set_led_para = 0;
                Utils::_led_para_init_mutex.unlock();
            }
            return ;
        }
    }else if(g_set_led_para == 2){
#if 0
        g_freeze_out = 1;
        Utils::_led_para_init_mutex.lock();
        g_set_led_para = 0;
        g_set_led_setup = 0;
        Utils::_led_para_init_mutex.unlock();

        /*if((SPLIT_8_to_16(p_ram0_u8,LED_INFO_OCH_MODE) & 0x01)  == 0x00 ){

                SCREEN_fpgactrl_status(VBYONE_NO_DIV_MODE);

            }else{
                SCREEN_fpgactrl_status(VBYONE_SPLICE_MODE);

            }*/

        set_led_para_ticks = G_timeTicks;
        SCREEN_fpgactrl_status(VBY_DECODE_STATUS);
        set_led_check_times = 0;
#else
        // 由于最新的FPGA 在设置屏参时没有办法正常（9月13号的正常），没有办法，现在直接重启后级
        Utils::_led_para_init_mutex.lock();
        g_set_led_para = 0;
        g_set_led_setup = 0;
        Utils::_led_para_init_mutex.unlock();

        reset_fpga_rst(FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
        reset_fpga_rst(FPGA_MASTER_VBYONE2);
#endif
#endif
        return ;
    }else if(g_freeze_out ==1){
        /*if(Utils::getTimeSpace(set_led_para_ticks) > 350){
            SCREEN_fpgactrl_status(SCREEN_LIGHT);
            g_freeze_out = 0;
            Utils::_led_para_init_mutex.lock();
            g_set_led_para = 0;
            Utils::_led_para_init_mutex.unlock();
        }*/
        if(g_set_led_setup == 0){
            if(Utils::getTimeSpace(set_led_para_ticks) > 20){
                if(((MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE0_REG]& 0x04) == 0)
        #if (defined OUTPUT_BOARD_2)
                        &&
                        ((MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE0_REG]& 0x04) == 0)
        #endif
                        ){
                    //                    g_freeze_out = 0;
                    Utils::_led_para_init_mutex.lock();
                    g_set_led_setup = 1;
                    Utils::_led_para_init_mutex.unlock();
                }else{
                    set_led_check_times++;
                    SCREEN_fpgactrl_status(VBY_DECODE_STATUS);

                    if(set_led_check_times > 500){
                        //                        g_freeze_out = 0;
                        Utils::_led_para_init_mutex.lock();
                        g_set_led_setup = 1;
                        Utils::_led_para_init_mutex.unlock();
                    }
                }
                set_led_para_ticks = G_timeTicks;
            }
        }else if(g_set_led_setup == 1){
            if(Utils::getTimeSpace(set_led_para_ticks) > 20){
                //            if((SPLIT_8_to_16(p_ram0_u8,LED_INFO_OCH_MODE) & 0x01)  == 0x00 ){
                SCREEN_fpgactrl_status(VBYONE_NO_DIV_MODE);
                //            }else{
                //                SCREEN_fpgactrl_status(VBYONE_SPLICE_MODE);
                //            }
                Utils::_led_para_init_mutex.lock();
                g_set_led_setup = 2;
                Utils::_led_para_init_mutex.unlock();
                set_led_para_ticks = G_timeTicks;
            }
        }else if(g_set_led_setup == 2){
            if(Utils::getTimeSpace(set_led_para_ticks) > 20){
                /*if((SPLIT_8_to_16(p_ram0_u8,LED_INFO_OCH_MODE) & 0x01)  == 0x00 ){
                    //
                    SCREEN_fpgactrl_status(ENABLE_LCD);
//                    g_freeze_out = 0;
                    Utils::_led_para_init_mutex.lock();
                    g_set_led_setup = 4;
                    Utils::_led_para_init_mutex.unlock();
                    set_led_check_times = 0;
                }else*/{
                    SCREEN_fpgactrl_status(VBYONE_SPLICE_MODE);
                    Utils::_led_para_init_mutex.lock();
                    g_set_led_setup = 100;//3;
                    Utils::_led_para_init_mutex.unlock();
                    set_led_para_ticks = G_timeTicks;
                }
            }
        }

        else if(g_set_led_setup == 100){
            if(Utils::getTimeSpace(set_led_para_ticks) > 20){
                {
                    //SCREEN_fpgactrl_status(VBYONE_SPLICE_MODE);
                    //设置屏参过程可能引起第一行不对的问题，OVP_G32_F0_V23071332--DIV2-1-FIR.FCG
                    write_to_register(FPGA_CLEAR_REG,0x20,0x20,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
                    write_to_register(FPGA_CLEAR_REG,0x20,0x20,FPGA_MASTER_VBYONE2);
#endif
                    Utils::_led_para_init_mutex.lock();
                    g_set_led_setup = 99;
                    Utils::_led_para_init_mutex.unlock();
                    set_led_para_ticks = G_timeTicks;
                }
            }
        }

        else if(g_set_led_setup == 99){
            if(Utils::getTimeSpace(set_led_para_ticks) > 20){
                {
                    //SCREEN_fpgactrl_status(VBYONE_SPLICE_MODE);
                    //设置屏参过程可能引起第一行不对的问题，OVP_G32_F0_V23071332--DIV2-1-FIR.FCG
                    write_to_register(FPGA_CLEAR_REG,0x20,0x00,FPGA_MASTER_VBYONE1);
#if (defined OUTPUT_BOARD_2)
                    write_to_register(FPGA_CLEAR_REG,0x20,0x00,FPGA_MASTER_VBYONE2);
#endif
                    Utils::_led_para_init_mutex.lock();
                    g_set_led_setup = 3;
                    Utils::_led_para_init_mutex.unlock();
                    set_led_para_ticks = G_timeTicks;
                }
            }
        }



        else if(g_set_led_setup == 3){
            if(Utils::getTimeSpace(set_led_para_ticks) > 20){
                SCREEN_fpgactrl_status(ENABLE_LCD);
                //                g_freeze_out = 0;
                Utils::_led_para_init_mutex.lock();
                g_set_led_setup = 4;
                Utils::_led_para_init_mutex.unlock();
                set_led_check_times = 0;
            }
        }else if(g_set_led_setup == 4){
            if(Utils::getTimeSpace(set_led_para_ticks) > 10){
                if(((MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE0_REG]& 0x80) == 0x80)
        #if (defined OUTPUT_BOARD_2)
                        &&
                        ((MCU_REG_func[FPGA_MASTER_VBYONE2][FPGA_STATE0_REG]& 0x80) == 0x80)
        #endif
                        ){
                    g_freeze_out = 0;
                    SCREEN_fpgactrl_status(SCREEN_LIGHT);
                    Utils::_led_para_init_mutex.lock();
                    g_set_led_setup = 0;
                    Utils::_led_para_init_mutex.unlock();
                }else{
                    set_led_check_times++;
                    SCREEN_fpgactrl_status(VBY_DECODE_STATUS);

                    if(set_led_check_times > 500){
                        g_freeze_out = 0;
                        SCREEN_fpgactrl_status(SCREEN_LIGHT);
                        Utils::_led_para_init_mutex.lock();
                        g_set_led_setup = 0;
                        Utils::_led_para_init_mutex.unlock();
                    }
                }
                set_led_para_ticks = G_timeTicks;
            }

        }
        return ;
    }

    return ;
}


Ouint32 fpga_manage::get_wlan_state()
{
    Ouint32 wlan_state = 0;

    Ouint16 temp1  = 0;
    if(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_INIT_OK] == 0x03){
        read_from_register(FPGA_STATE1_REG,FPGA_MASTER_VBYONE1);
        read_from_register(FPGA_STATE3_REG,FPGA_MASTER_VBYONE1);
        temp1 = (MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG]<<8)|MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG];
    }

    wlan_state = temp1;



    //    BX_printf("\n FPGA_STATE1_REG : %d, FPGA_STATE3_REG : %d\n",MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE1_REG],MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_STATE3_REG]) ;
    //    BX_printf("\n wlan_state : 0x%x\n",wlan_state) ;

    return wlan_state;
}


void fpga_manage::check_wlanonline_state()
{

}

string fpga_manage::checkVersion()
{
    Oint32 year = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE3_REG]);
    Oint32 month = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE2_REG]);
    Oint32 date = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE1_REG]);
    Oint32 fuc = BCD_to_HEC(MCU_REG_func[FPGA_MASTER_VBYONE1][FPGA_BYTE0_REG]);
    string version = Utils::intToString(year,2) + Utils::intToString(month,2) + Utils::intToString(date,2) + Utils::intToString(fuc,2);
    // BX_printf("\n version = %s \n",version.data());
    return version;
}






